Investigation into SEU Effects and Hardening Strategies in SRAM Based FPGA

Abstract

The mitigation of single event upset (SEU) in SRAM based Field Programmable Gate Array (FPGA) is increasingly important as it is widely used in radiation environments such as space. As D flip-flop (DFF) and memory (including Block RAM and Configuration RAM) are the key elements in FPGAs, it is crucial to develop radiation hardening techniques for enhanced reliability of the DFF and memory. A novel hardened memory design for FPGA is proposed with multi-bit upset (MBU) protection. We further developed two prototype FPGA chips, one with and the other without SEU hardening for comparison. The FPGA chips are fabricated in a standard 0.13μm CMOS process and have a volume of 3 million equivalent logic gates. In contrast to the base FPGA, the SEU cross section of the memory in the hardened FPGA is at least three orders of magnitude lower. Also, no SEU upsets are observed in the DFF of the hardened FPGA.