Clock Tree Optimization of FPGA Semi-Custom Memory with SEU FlipFlops

Abstract

Flip-flops (FFs) and memory (including Block RAM and Configuration RAM) are the key elements in Field Programmable Gate Arrays (FPGA). A single radiation event can flip the storage node of the sequential elements. FPGAs are widely used in radiation environments such as space, the mitigation of single event upset (SEU) in SRAM based FPGAs is increasingly important. Generally, the SRAM macros implement well optimized in-built Error Correction Codes (ECC). For SEU tolerance, traditional FFs are replaced by SEU hardened FFs. SEU FFs have higher setup and clock-to-out delays and degrades the performance of SRAMs in FPGAs.High performance SRAMs in FPGAs are implemented using Hybrid approach of custom and PNR (Place and Route). FPGA applications demanding more features such as ability to form deeper memories, and the programmable word size etc. This leads to increase in the logic and wirelengths, which further introduces higher delays in designs and impacts performance.So, the optimal clock-distribution network in high density memories along with SEU tolerance features, is one of the key aspects of high-speed SoC designs. This paper demonstrates methods to implement high quality clock tree to mitigate delay penalties introduced by the SEU hardened FFs and higher wirelengths. Experimental results demonstrate that the proposed approach significantly improves clock tree performance.