Abstract
Effects of Single Event Upsets (SEU) and Single Event Transients (SET) are studied in the FE-I4B chip of the innermost layer of the ATLAS pixel system. SEU/SET affect the FE-I4B Global Registers as well as the settings for the individual pixels, causing, among other things, occupancy losses, drops in the low voltage currents, noisy pixels, and silent pixels. Quantitative data analysis and simulations indicate that SET dominate over SEU on the load line of the memory. Operational issues and mitigation techniques are presented.
Highlights
The ATLAS Pixel detector, including the IBL, was operated efficiently at high luminosity, and Single Event Upsets (SEU) were observed at rates close to the expectation based on previous tests in 24 GeV proton beam
SEUs in the global and local pixel configuration memories of FE-I4B chip were observed during LHC fills and had several consequences: module de-synchronization, current jumps, dead modules, quiet pixels, noisy pixels, broken clusters, etc
By read-back measurements and simulations of the electronics, it was demonstrated that Single Event Transients (SET) on the LOAD line of the DICE latch dominate the memory flips
Summary
The original ATLAS Run 1 Pixel detector was upgraded for Run 2 with the addition of the IBL, which provides an additional layer of pixels at ∼ 3.4 cm from the interaction point. The IBL detector consists of one layer of pixel sensors (see figure 4) built around the beam pipe, providing full azimuthal (φ) hermeticity for high transverse momentum (pT > 1 GeV) particles and longitudinal coverage up to |η| = 3. The IBL readoR2u3t.5e- Ilnencertrbeoanmi-pcispeare designed to exploit the enhanced detector performance and overcome the limitaR3t1i.o0n- IsBLpinrneerseennvetloipne ATLAS Pixel Run 1 sysSttaevme fl.exThe IBL readout system consists R40.0 - IBL outer envelope of two 9U-VME caRr3d3.5s:- MtohdueleBradaiucsk-of-Crate (BOC) and ReadSt-aOve ut Driver (ROD) which implement optical I/O interface and data processing, respectively (see fiFEg-Iu4Brechi8p ). Further details about the IBL detector layout and naming convention are covered in the appendix, including the naming schemes used for the power system, the data-acquisition modules, the sensors, and the front end chips
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