Characterization and Mitigation of Single-Event Transients in Xilinx 45-nm SRAM-Based FPGA

Abstract

This paper presents a new approach for analyzing the effect of single-event transient (SET) in SRAM-based field-programmable gate array (FPGA) devices, which are widely used in the space environment. New SET characterizing and mitigation techniques, including continuous monitoring and controlling of the test, are proposed to ensure proper operation of the device under test. This is vital for verifying the proper functioning of the design and performing online reconfiguration if required, since the effect of a single-event upset (SEU) on the device configuration bits may disrupt the SET detection and mitigation design. While many studies focus on SEU, latch-up, and cumulative radiation [total ionizing dose (TID)] effects on SRAM-based FPGAs, only a few published works refer to the SET effect. Moreover, in contrast to previous SET studies, this paper presents a quantitative assessment for SET probability under the real radiation environment and provides cross-sectional analysis for both SET and SEU effects at low linear energy transfers (LETs) (up to 0.925 MeV $\cdot$ cm2/mg). The SET experiments have been carried out at UCL Cyclotron (Belgium) accelerator using heavy ions and under alpha source irradiation. Experimental results indicate that SET examinations on SRAM-based FPGAs should be performed only at low LETs due to the high SEU rate compared to the SET rate. Several kinds of filters have been implemented and proposed for SET mitigation demonstrating a significant reduction of the SET transient effects. The proposed methodology may provide a basic model for future research studies on SET radiation effects on SRAM-based FPGAs, and assisting in selecting an immune FPGA-based platform for satellites applications.