Memory State Transient Analysis (MSTA): A New Soft Error Rate Measurement Method for CMOS Memory Elements Based on Stochastic Analysis

Abstract

We analyze the evolution of SRAM memory logic contents under irradiation by defining the memory state as the number of cells storing a given logic value (i.e. number of cells storing a logic-1). We find that the memory state evolution under irradiation follows an Ehrenfest urn model due to the constant effect of single event upsets, and that in large memories it can be associated to an Ornstein-Uhlenbeck process. Memory state transient analysis has been applied to determine the device Soft error rate for an SRAM fabricated in a 65 nm commercial CMOS process obtaining a very good correlation. Furthermore, our analysis shows that the technique is applicable to systems composed by various dissimilar memory components, providing–under certain circumstances–the specific Soft Error Rate of each component.