Self-heating Effect Research Articles

Design and Analysis of Nanosheet Field-Effect Transistor for High-Speed Switching Applications

Self-heating effects and short channel effects are unappealing side effects of multigate devices like gate-all-around nanowire-field-effect transistors (FETs) and fin FETs, limiting their performance and posing reliability difficulties. This paper proposes the use of the novel nanosheet FET (NsFET) for complementary metal-oxide semiconductor technology nodes that are changing. Design guidelines and basic measurements for the sub-nm node are displayed alongside a brief introduction to the roadmap to the sub-nm regime and electronic market. The device had an ION/IOFF ratio of more than 105, according to the proposed silicon-based NsFET. For low-power and high-switching applications, the results were verified and achieved quite well. When an NS width increases, although, the threshold voltage (Vth) tends to fall, resulting in a loss in subthreshold effectiveness. Furthermore, the proposed device performance, like subthreshold swing ION/IOFF, was studied with a conventional 2D FET. Hence, the proposed NsFET can be a frontrunner for ultra-low power and high-speed switching applications.

Investigation of Analog/RF and linearity performance with self-heating effect in nanosheet FET

In vertically stacked gate-all-around Nanosheet FET (NSFET), the channels/sheets are wrapped by a low thermal conductivity material, which hinders the active heat flow path and, thus, raises reliability concerns. Therefore, the role of temperature, i.e., ambient condition and self-heating effect (SHE), become prime objectives that must be adequately addressed. In this work, through extensive TCAD simulations, we analyzed the DC/Analog/RF/Linearity characteristics of an NSFET, considering the cumulative effect of ambient temperature and SHE. Using well-calibrated TCAD models, we investigated: (i) the variation in device characteristics with and without considering SHE; (ii) the impact of SHE and ambient temperature on Analog/RF and Linearity characteristics using well-defined figure-of-merits (FoMs); (iii) the device optimization, i.e., the significance of the varying number of sheets (Nsheet) with considering SHE for optimal performance; (iv) the impact of varying temperature over the voltage gain of an NSFET-based common source (CS) amplifier considering SHE. The temperature variation (including SHE) significantly affects the ON current (e.g., reduced by 9.4%), resulting in the modulation in transconductance (gm). Therefore, the designed CS amplifier's gain is also altered by temperature variation (e.g., ranging from 250 K to 400 K). Hence, the proposed analysis is worth exploring to acquire the design guidelines for optimal and reliable DC/Analog/RF/Linearity characteristics of a Nanosheet transistor under various temperature conditions.

P-type trench gate based drain-extended N-type MOS design for high unclamped inductive switching reliability

The drain-extended NMOS (DeNMOS) is a low-voltage power MOSFET. It comprises intrinsic parasitic BJT (P-BJT), which can trigger under the influence of lattice heating or avalanche-generated holes. The parasitic bipolar current and self-heating effect (SHE) facilitates the second breakdown phenomena near the drain. Hence, we proposed DeNMOS with a P-type trench gate (PTG) placed between the body and source contact to optimize the P-BJT and SHE at high current conditions using the Sentaurus TCAD simulator tool. The PTG increases hole accumulation within the P-body region to optimize the bipolar effect. Furthermore, the proposed DeNMOS (PTG_DeNMOS) structure incorporates an additional heat dissipation path, improving the thermal stability of the device. It is shown that mitigating the P-BJT enhances the device avalanche ruggedness and unclamped inductive switching (UIS) reliability at high current conditions. The analyzed results show that the proposed PTG_DeNMOS ensures UIS reliability at a peak current density 35% higher than the conventional DeNMOS (C_DeNMOS) without compromising mixed signal performance.

Thermal phonon modulation of III-nitride semiconductors under strong electric fields

Self-heating effects in high-power III-nitride semiconductor electronics and optoelectronic devices limit their practical applications, while phonon modulation can be used to alleviate heat dissipation problems. In this paper, we report our efforts to suppress macroscopic polarization fields when applying strong electric fields, which affect the phonon frequency. We investigate alterations in phonon frequencies for two materials, 2H-GaN and 2H-AlN, for various electric field strengths ranging from 0.00 V/Å to 0.07 V/Å and 0.00 V/Å to 0.18 V/Å, respectively. We also analyze the changes in the macroscopic dielectric tensor and the BORN effective charge tensor. The calculation results reveal that the vibration frequencies of the longitudinal-optical (LO) A1(LO) mode are decreased by approximately 2 cm−1 for 2H-GaN and 3 cm−1 for 2H-AlN. Our simulation results are consistent with the Raman spectroscopy results of Si-doped 2H-GaN specimens illuminated with 325 nm excitation for a variety of carrier concentrations. This study contributes to a better understanding of the factors influencing phonon behavior, thus offering new methods for optimizing the thermal regulation and dissipation patterns of III-nitride semiconductor materials and devices.

Improved self-heating extraction with RF technique at cryogenic temperatures

This work studies self-heating effect using the modified RF characterization technique at cryogenic temperatures down to 77 K. It is shown that neglecting the transition related to the substrate effect in the output conductance frequency response can result in a strong underestimation of the thermal resistance, especially at bias conditions close to the threshold voltage (Vth) region and alter its temperature, length and bias dependencies which is important to consider for device modelling.

Optimization of vertically stacked nanosheet FET immune to self-heating

The self-heating effect (SHE) is one of the major challenges of ultra-scaled devices such as stacked nanosheet field effect transistor (SNSHFET) for sub 7 nm technology. The DC performance metrics of vertically SNSHFET are investigated and quantified against various geometrical parameters in the perspective of self-heating. Impact of self-heating is higher for larger gate and supply voltages. An average electron velocity reduction of 25 × 103 m/s and average electron mobility degradation of 242 cm2 V−1s−1 with SHE is observed for 5 nm thickness and 50 nm wider nanosheet. The increase in nanosheet width (WNSH) and thickness (tNSH), enhances device lattice temperature (TL) and other impediments. The results shows for the optimized device geometry, the SNSHFET exhibits better performance with immune to self-heating.

A large-area multi-finger β-Ga2O3 MOSFET and its self-heating effect

The self-heating effect severely limits device performance and reliability. Although some studies have revealed the heat distribution of β-Ga2O3 MOSFETs under biases, those devices all have small areas and have difficulty reflecting practical conditions. This work demonstrated a multi-finger β-Ga2O3 MOSFET with a maximum drain current of 0.5 A. Electrical characteristics were measured, and the heat dissipation of the device was investigated through infrared images. The relationship between device temperature and time/bias is analyzed.

On the Practical Limitations for the Generation of Gunn Oscillations in Highly Doped GaN Diodes

Planar Gunn diodes based on doped GaN active layers with different geometries have been fabricated and characterized. Gunn oscillations have not been observed due to the catastrophic breakdown of the diodes for applied voltages around 20–25 V, much below the bias theoretically needed for the onset of Gunn oscillations. The breakdown of the diodes has been analyzed by pulsed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{I}$</tex-math> </inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}$</tex-math> </inline-formula> measurements at low temperatures, and it has been observed to be almost independent of the geometry of the channels, thus allowing to discard self-heating effects as the origin of the device burning. The other possible mechanism for the device failure is an impact-ionization avalanche due to the high electric fields present at the anode corner of the isolating trenches. However, Monte Carlo simulations using the typical value of the intervalley energy separation of GaN, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\varepsilon_{\text{1}-\text{2}}$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula> 2.2 eV, show that impact ionization mechanisms are not significant for the voltages for which the experimental failure is observed. But recent experiments showed that <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\varepsilon_{\text{1}-\text{2}}$</tex-math> </inline-formula> is lower, around 0.9 eV. This lower intervalley separation leads to a much lower threshold voltage for the Gunn oscillations, not far from the experimental breakdown. Therefore, we attribute the device’s failure to an avalanche process just when Gunn domains start to form, since they increase the population of electrons at the high electric field region, thus strongly enhancing impact ionization mechanisms that lead to the diode failure.

Equivalent circuit model of GaN high electron mobility transistor with consideration of non-ideal effects using genetic algorithm

This work proposes a semi-physical equivalent circuit model for GaN-based high electron mobility transistors (GaN HEMTs), taking into account the non-ideal effects of both the current source and resistance–capacitance components. The current source model is built based on both device operation and multiple model interfaces setup for important non-ideal effects, such as self-heating effects, channel length modulation, short channel effects, and so on. Moreover, according to the improved Meyer capacitance model with fringe capacitances, the non-linear capacitances of the GaN HEMT are modeled with a dependence on the bias voltages and gate geometry. The extraction of the model parameters is implemented accurately and efficiently in MATLAB through a genetic algorithm. Moreover, the capacitance model is established to be mathematically simple and Simulation Program with Integrated Circuit Emphasis (SPICE)-compatible for the design of GaN-based integrated circuits (ICs). The static and dynamic characteristics of GaN ICs were simulated and found to be in excellent agreement with the experimental results, validating that the established and well-packaged equivalent circuit model can be of great help to GaN HEMT development and IC design.

Dipolar and anisotropy effect on dextran coated Cu doped ferrite for magnetic hyperthermia applications

The dipolar interaction and magnetic anisotropy effect are the key parameters to tune the self-heating effect of magnetic nanoparticles (MNPs). In this paper, we investigate the impact of Cu2+ doped Fe3O4 and dextran coated nanoparticles (CuxFe3-xO4 with x = 0.15, 0.31, and 0.47) on thermal properties using specific absorption rate measurements (SAR). We look into the prospect of using dipolar and anisotropy effects to increase or decrease the heat released by magnetic nanoparticles, potentially boosting hyperthermia applications. Magnetic nanoparticles with an average particle size of 12–20 nm were observed via TEM. The influence of Cu2+ doping on the structural and magnetic properties of the samples was studied using a vibrating sample magnetometer (VSM). The effective anisotropy calculated for x = 0.15 and x = 0.47 were 5.5 and 4.4 j/m3 respectively. It was shown that increasing the copper doping reduced the effective anisotropy, lowering the SAR values. The SAR value obtained for x = 0.15 and dex-x = 0.15 were 787 and 591 W/g respectively. The uncoated CuxFe3-xO4 nanoparticles achieved hyperthermia temperatures (42–48 °C) much faster than the dextran-coated samples. Eventually temperature can be adjusted to the desired hyperthermia temperature range by altering the sample and Cu2+ concentration. The dextran coating has been shown to dramatically reduce SAR values while still assisting in magnetic hyperthermia temperature regulation. The study also demonstrated that the dipolar interaction influenced the Néel relaxation mechanism which was important in the heat generation mechanism of the MNPs

A suggested nanoscale partially depleted SOI-MOSFET (PDSOI) by built-in tunneling diodes- improvement on short channel effects and frequency features

This paper describes a new modified structure based on partially depleted silicon-on-insulator (PDSOI) MOSFETs with built-in tunneling diodes inside the buried oxide. This action will change the electric field and create a new path for the accumulated holes to be evacuated. Hence, the floating body effect (FBE), which is a very harmful event, is successfully controlled by these built-in diodes. The diodes will be formed by inserting N+ and P+ doping regions inside the buried oxide, which will provide both vertical and lateral holes for current tunneling through the channel region. Furthermore, with the introduction of the tunneling diode inside the buried oxide, the effective thermal conduction of the proposed device increases, eventually resulting in a reduction of the self-heating effect. Two parameters in the cases of reduced self-heating effect and FBE gave the suggested structure a potent capability to gain further figure of merits in the terms of subthreshold swing, leakage current, ION/IOFF, drain-induced barrier lowering (DIBL), power gains, drain-source conductance, cut-off frequency, and minimum noise figure. The device has been simulated by the ATLAS tools from the SILVACO family and compared with the conventional structure. All the obtained results displayed the privilege of the proposed device as compared to the common device.

Substrate Biasing Effect in a High-Voltage Monolithically-Integrated GaN-on-SOI Half Bridge With Partial Recessed-Gate HEMTs

The physical mechanism of the substrate biasing effect (SBE) in a high-voltage monolithically-integrated GaN-on-SOI half bridge with partial recessed-gate high-electron-mobility transistors (HEMTs) is comprehensively analyzed by TCAD simulation. The SBE originates from the capacitive coupling of the buffer layer and the buffer traps, which can be effectively suppressed by the GaN-on-SOI platform with the top Si shorted to the source technology. The simulations show that the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{ON}}$</tex-math> </inline-formula> of high side HEMT on the GaN-on-SOI platform with the top Si shorted to the source is 0.223 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\bm{\Omega}$</tex-math> </inline-formula> and does not degrade with the bus voltage increase, while the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{ON}}$</tex-math> </inline-formula> increases from 0.223 to 0.900 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\bm{\Omega}$</tex-math> </inline-formula> for the case on GaN-on-Si platform when the bus voltage increases to 400 V. In addition, for GaN-on-SOI platform with the top Si shorted to the source of HEMTs, the crosstalk can be effectively suppressed and the self-heating effect does not aggravate. Moreover, the integrated half bridge on GaN-on-SOI platform with the top Si shorted to the source shows lower overshoot current, tail current and switching power consumption compared to the half bridge made of two discrete HEMTs on GaN-on-Si platform.

Interfacial trap charge and self-heating effect based reliability analysis of a Dual-Drain Vertical Tunnel FET

This manuscript exclusively addresses the reliability concern of a double-drain vertical TFET (DD-VTFET) by analysing the influence of interface trap charges and variation in ambient temperature on various DC and analog/RF figure of merits. For detailed analysis, performance of the device is evaluated by considering different densities and polarities of trap charges existing at gate-oxide/channel interface. TCAD-based simulation results reveal that trap charges significantly alter the flat-band voltage, which further causes variation in the device performance. It is observed from the transfer characteristic curve that the leakage current is degraded from 10−18 to 10−13A/μm when a positive (donor) charge density of 1013 cm−2 is introduced at oxide/channel interface. However, cut-off frequency is found to be improved under the influence of donor traps, which is mainly attributed due to improvement in transconductance of the device. Moreover, simulation results indicate that DD-VTFET is immune to the negative (acceptor) traps in comparison with the positive traps. Furthermore, the analysis carried out for temperature affectability on the device performance suggests that, at higher ambient temperature, the off-state current degrades more in subthreshold region (at low gate bias) due to dominance of the Shockley-Read-Hall (SRH) and trap-assisted tunneling (TAT) mechanisms, which exponentially depend on the temperature. Therefore, the leakage current increases approximately by an order 7 when temperature is increased from 200 K to 400 K. Since band-to-band tunneling starts dominating over SRH and TAT in the super-threshold region (at high gate bias), the impact of temperature variation along with presence of the trap charges is found to be insignificant on the transfer characteristics.

Combined Influence of Gate Oxide and Back Oxide Materials on Self-Heating and DIBL Effect in 2D MOS2-Based MOSFETs

In this paper, degradation effects, such as self-heating effect (SHE) and drain-induced barrier lowering (DIBL) effect in 2D MoS2-based MOSFETs are investigated through simulations. The SHE is simulated based on the thermodynamic transport model. The dependence of the DIBL effect and the lattice temperature in the middle of the channel on the gate length is considered for transistors with different gate oxide and back oxide (BOX) materials. The effects of Al2O3 and HfO2 as gate oxide and SiO2 and HfO2 as BOX materials are compared. Transistors, in which the channel is fully and partially (i.e., just below the gate) covered by a gate oxide, are considered. It is shown that the transistors with Al2O3 as gate oxide and SiO2 as BOX materials have higher immunity to DIBL effect and transistors with HfO2 as gate oxide and HfO2 as BOX materials have higher immunity to SHE.

Study of Self Heating Effect in the wake of complete and partial bottom dielectric insertion under 5 nm Stacked Nanosheet Transistor

Beyond 7 nm technology nodes, a Stacked Nanosheet Field Effect Transistor (SNT) is a potential candidate to continue device scaling due to its higher ON/OFF current ratio and less Short Channel Effect than FinFET. However, its gate all-around structure with low thermal conductive HiK oxide material exacerbates the Self-Heating Effect (SHE) issue in the SNT. Further, a dielectric inserted beneath SNT to reduce leakage current disrupts the primary heat flow path through the substrate, aggravating the Self Heating Effect (SHE). This study focuses on exploring the thermal aspect of the SNT with partial and complete dielectric insertion under the device from a performance and reliability perspective. A 3D electrothermal analysis has been performed using Synopsys TCAD tool. The effect of partial and complete dielectric insertion under the device on lattice temperature was investigated in the case of single and double-stack nanosheet transistors. The effects of dielectric insertion on channel and substrate temperature were analyzed. Its variation with width, extension length, interface thermal resistance, and the number of sheets and stack pitch of SNT are discussed. Sheet-dependent heat flow through the substrate and source/drain contact explained for different types of SNT structures and its effect on device performance and reliability discussed. To discuss the effect of multiple parameters variation on the lattice temperature of the device, Analysis of Variance (ANOVA) method was used. It was found that complete dielectric insertion leads to a severe heating issue in the SNT compared to partial and without dielectric insertion.

Polarization-independent high contrast grating 1300 nm dot-in-a-well InAs quantum-dot VCSEL

High contrast grating (HCG) 1300 nm InAs/GaAs quantum dot (QD) vertical-cavity surface-emitting laser (VCSEL) has been introduced in this manuscript and the impact of device structure on the self-heating effect and device temperature has been investigated. A self-consistent model that couples the opto-electro-thermal model of the device to the optical gain model is used to calculate optical gain. Simulated results indicate that the proposed structure significantly lowers the hole-burning effect due to a decrease in temperature. So, in contrast to the conventional QD-VCSELs, the HCG QD-VCSEL exhibits better carrier confinement due to hole quantum efficiency of 54% as opposed to 45% for the conventional QD-VCSELs at their rollover current density. Also, results show an improvement of 66% in the maximum output power from the HCG QD-VCSEL compared to a conventional QD-VCSEL structure. In addition, the 3-dB modulation bandwidth has been boosted compared to conventional QD-VCSELs.

Recent Advances on GaN-Based Micro-LEDs.

GaN-based micro-size light-emitting diodes (µLEDs) have a variety of attractive and distinctive advantages for display, visible-light communication (VLC), and other novel applications. The smaller size of LEDs affords them the benefits of enhanced current expansion, fewer self-heating effects, and higher current density bearing capacity. Low external quantum efficiency (EQE) resulting from non-radiative recombination and quantum confined stark effect (QCSE) is a serious barrier for application of µLEDs. In this work, the reasons for the poor EQE of µLEDs are reviewed, as are the optimization techniques for improving the EQE of µLEDs.

Channel Temperature Analysis and Nonlinear Thermal Model of AlGaN/GaN HEMTs Including Steady-State and Transient

The thermal analysis of GaN-based high electron-mobility transistors (HEMTs) is carried out from steady-state and transient aspects, respectively. An improved closed-form nonlinear thermal model based on device structure is proposed. In the steady-state case, the plane layer is added on the basis of the original partition, and the effect of thermal boundary resistance on channel temperature is also considered. In addition, the operating temperature of each gate finger is predicted based on the thermal coupling, and the nonlinear thermal model is extended to the transient by combining the thermal time constant. The validity of our presented model is verified by comparing the simulation results with the experimental data. Furthermore, this model is also embedded in the surface-potential-based current model to verify the self-heating effect in the circuits.

Electrothermal analysis of a TEC-less IR microbolometer detector including self-heating and thermal drift

ABSTRACT The article presents the results of modelling and experiments of the self-heating and thermal drift effects of microbolometric sensors of infrared radiation. The developed electrothermal model of the readout electronic circuit generates the power dissipated in the active microbolometer during row-by-row scanning implemented in the focal plane array (FPA) detector. Two approaches to thermal modelling are presented. Both 1D frequency domain and 2D time domain finite element method models allow estimation of the thermal behaviour of an FPA microbolometer. The modelling and presented experiment results lead to the estimation of the deterioration in FPA performance and allow definition of the basic limits of resistive bolometers in operation.

Spectral behavior of high-power distributed feedback lasers

The mode hopping behavior of high-power distributed feedback lasers emitting near 780,hbox {nm} is studied. The lasers have highly reflective rear and anti-reflection coated front facets. The influence of the phase of the grating at the rear facet is investigated by means of numerical simulations in the time domain taking into account spatial hole burning and self-heating effects. The simulation results are in agreement with experimental findings.