Effect Of Dielectrics Research Articles

Effect of Dielectric Interface on the Performance of MoS2 Transistors.

Because of their wide bandgap and ultrathin body properties, two-dimensional materials are currently being pursued for next-generation electronic and optoelectronic applications. Although there have been increasing numbers of studies on improving the performance of MoS2 field-effect transistors (FETs) using various methods, the dielectric interface, which plays a decisive role in determining the mobility, interface traps, and thermal transport of MoS2 FETs, has not been well explored and understood. In this article, we present a comprehensive experimental study on the effect of high-k dielectrics on the performance of few-layer MoS2 FETs from 300 to 4.3 K. Results show that Al2O3/HfO2 could boost the mobility and drain current. Meanwhile, MoS2 transistors with Al2O3/HfO2 demonstrate a 2× reduction in oxide trap density compared to that of the devices with the conventional SiO2 substrate. Also, we observe a negative differential resistance effect on the device with 1 μm-channel length when using conventional SiO2 as the gate dielectric due to self-heating, and this is effectively eliminated by using the Al2O3/HfO2 gate dielectric. This dielectric engineering provides a highly viable route to realizing high-performance transition metal dichalcogenide-based FETs.

Investigation on the effect of dielectrics during micro-electro-discharge machining of Ti-6Al-4V

Machining of micro-holes using micro-electro-discharge machining (micro-EDM) is an important field of micro-manufacturing technique. Micro-holes are essential features in optical devices, medical instruments, and automobile engine parts. Micro-EDM has been considered as the best non-traditional machining technique for generating micro-holes on high strength temperature resistant, and difficult to machine advanced materials such as Ti-6Al-4V. Ti-6Al-4V is a widely used material in aerospace and chemical industries. However, machining of micro-holes on Ti-6Al-4V using micro-EDM process is not fully explored. In this study, emphasis has been made to experimentally investigate the influence of various types of dielectrics, such as DEF-92 (EDM oil), pure deionized water, and Cu powder mixed deionized water on micro-EDM process response parameters, such as material removal rate (MRR), tool wear rate (TWR), overcut (OC), and taper during micro-hole machining of Ti-6Al-4V. It is observed that Cu powder mixed deionized water significantly improves the machining performance of the micro-EDM process. Furthermore, the machined profile and topography of the micro-hole obtained with Cu powder mixed deionized water is found to be better as compared to those machined with EDM oil or pure deionized water.

Effect of Different Dielectrics on Material Removal Rate, Electrode Wear Rate and Microstructures in EDM

Diesinker electric discharge machining is widely used non-conventional technique for making high precision and complex shaped parts. Dielectrics and electrical parameters were considered as the main factors for EDM performance. In this paper, the effects of pulse-on-time (μs) and current (ampere) were evaluated for performance measures using kerosene and water as dielectrics. A comparison was performed for both dielectrics in terms of material removal rate (mm3/min), electrode wear rate (mm3/min), and microstructures. Aluminum 6061 T6 alloy was used as material for this research due to its extensive use in aerospace and automotive industries. Experiments were designed using Taguchi L9 orthogonal array (OA). Time series graphs were plotted to compare material removal rate and electrode wear rate. Microstructures were taken by scanning electron microscope to analyze the surface produced in terms of cracks, globules and micro-holes. Higher material removal rate and lower electrode wear were achieved with kerosene dielectric. The novelty of this research work, apart from its practical application, is that Aluminum 6061 T6 alloy is used as work material to compare the performance of dielectrics (kerosene and distilled water).

Auger and carrier-surface phonon interaction processes in graphene on a substrate made of polar materials

We present a theoretical study of two specific dynamical optical properties, namely Auger and surface electron-phonon interaction processes in monolayer graphene on polar substrates such asSiO2,HfO2,SiC and hexagonal BN. Thus the eigenenergies have been derived from the tight-binding Hamiltonian in monolayer graphene. Our results indicate that both Auger and electron-surface phonon interaction processes depend on the polar substrate. Such polar substrates allow for the presence of polar optical phonons localized near the graphene-substrate interface which could be a significant scattering source for graphene carriers across the long-range Fröhlich coupling. Furthermore, the linear, gapless band structure of graphene provides ideal conditions for Auger processes which are Auger recombination (AR) and impact ionization (IMI). These processes are of fundamental interest because they strongly influence the relaxation dynamics of carriers. Likewise, we have investigated the effect of various dielectrics on both Auger and electron–surface phonon scattering rates in single layer graphene by varying the temperature, the charge carrier density and the physical separation between the interface of the dielectric substrate and graphene.

Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations

In this paper, we propose a design of traditional sequential circuits using high performance Ballistic Deflection Transistor (BDT). BDT technology was developed and experimentally proven to operate at Terahertz frequencies. Different structures of BDTs have been developed successfully to realize combinational logic functionality. Monte Carlo (MC) simulations have been extensively used to study these structures. By taking into account the effect of surface charges and dielectrics, we are able to correctly reproduce the non-linear I-V transfer characteristics, to predict scaling down behavior and to estimate the very high switching speed. We then used a three parameter Gaussian peak as a predictive model for the BDT and integrated it with Verilog AMS module to confirm the functionality of the designed circuits. Finally, we used a recently developed level-sensitive D-latch using two-BDTs structure, to explore traditional sequential circuits such as Shift Registers (SRs), Frequency Divider and Johnson Ring Counter, which play a pivotal role in many processing systems as common datapath operators. The simulation results have indicated the correct logic functionality of the implemented sequential circuits.

Effect of Polymer Gate Dielectrics on Charge Transport in Carbon Nanotube Network Transistors: Low-k Insulator for Favorable Active Interface.

Charge transport in carbon nanotube network transistors strongly depends on the properties of the gate dielectric that is in direct contact with the semiconducting carbon nanotubes. In this work, we investigate the dielectric effects on charge transport in polymer-sorted semiconducting single-walled carbon nanotube field-effect transistors (s-SWNT-FETs) by using three different polymer insulators: A low-permittivity (εr) fluoropolymer (CYTOP, εr = 1.8), poly(methyl methacrylate) (PMMA, εr = 3.3), and a high-εr ferroelectric relaxor [P(VDF-TrFE-CTFE), εr = 14.2]. The s-SWNT-FETs with polymer dielectrics show typical ambipolar charge transport with high ON/OFF ratios (up to ∼105) and mobilities (hole mobility up to 6.77 cm2 V-1 s-1 for CYTOP). The s-SWNT-FET with the lowest-k dielectric, CYTOP, exhibits the highest mobility owing to formation of a favorable interface for charge transport, which is confirmed by the lowest activation energies, evaluated by the fluctuation-induced tunneling model (FIT) and the traditional Arrhenius model (EaFIT = 60.2 meV and EaArr = 10 meV). The operational stability of the devices showed a good agreement with the activation energies trend (drain current decay ∼14%, threshold voltage shift ∼0.26 V in p-type regime of CYTOP devices). The poor performance in high-εr devices is accounted for by a large energetic disorder caused by the randomly oriented dipoles in high-k dielectrics. In conclusion, the low-k dielectric forms a favorable interface with s-SWNTs for efficient charge transport in s-SWNT-FETs.

Effect of thin gate dielectrics on DC, radio frequency and linearity characteristics of lattice‐matched AlInN/AlN/GaN metal–oxide–semiconductor high electron mobility transistor

In this paper, the authors present a polarisation dependent analytical model for DC, radio frequency (RF) and linearity characteristics of a proposed lattice-matched AlInN/AlN/GaN metal–oxide–semiconductor high electron mobility transistor (MOSHEMT). The developed model includes charge controlled analysis derived from triangular potential well approximation along with the spontaneous and piezoelectric polarisation effects. The model accurately predicts the threshold voltage, two-dimensional electron gas sheet charge density, drain current, transconductance and cut-off frequencies for different samples of gate dielectric materials such as SiO2, HfO2 and Al2O3 over a full range of gate and drain bias. A detailed analysis of the linearity characteristics by investigating the key figure-of-merit metrics such as second-order voltage intercept point, third-order voltage intercept point, third-order input intercept point and third-order intermodulation distortion are performed for different gate dielectric thicknesses of 5, 7 and 10 nm. The accuracy of the model results is verified against Silvaco Technology Computer Aided Design numerical simulation results and found to be satisfactory. It is observed that by careful tuning the device parameters such as dielectric constant and dielectric thickness, lattice-matched AlInN/AlN/GaN MOSHEMT can considerably improve the device performance and suitable for high performance low distortion RF applications.

Full-solution-processed high mobility zinc-tin-oxide thin-film-transistors

The full solution-processed oxide thin-film-transistors (TFTs) have the advantages of transparency, ease of large-area fabrication, and low cost, offering great potential applications in switching and driving fields, and attracting extensive research interest. However, the performance of the solution-processed TFTs is generally lower than that of the vacuum-deposited ones. In this article, the full-solution processed TFTs with zinc-tin-oxide (ZTO) semiconductor and aluminium (Al2O3) dielectrics were fabricated, and their mobilities in the saturation region are high. Besides, the effect of the Al2O3 dielectrics’ preparation technology on ZTO TFTs’ performance was studied. Comparing the ZTO TFTs using the spin-coated Al2O3 dielectrics of 1–4 layers, the ZTO TFT with 3-layer Al2O3 dielectrics achieved the optimal performance as its field-effect carrier mobility in the saturation region is 112 cm2/V s, its threshold voltage is 2.4 V, and its on-to-off current ratio is 2.8×105. This is also the highest reported carrier mobility of the solution-processed ZTO TFTs.

Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET

In this paper, the impact of asymmetric gate stack architecture using a combination of vacuum and high-k dielectrics on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET has been investigated. A comparative evaluation of short channel effects (SCEs) for various device structures has also been carried out with figure of merit (FOM) metrics such as electric field, electron temperature, drain current (Ids), and drain induced barrier lowering (DIBL). A two-dimensional analytical model has been developed for the asymmetric architecture using Poisson’s equation in cylindrical coordinates assuming a parabolic potential profile. It is observed that the asymmetric gate stack device demonstrates effectiveness in suppressing hot carrier degradation and short channel effects along with improving the current drivability of the device as compared to the other device configurations. The analytical results have been verified with the simulated data obtained from ATLAS 3-D device simulator.

Investigation of the electron-surface phonon interaction effects in graphene on a substrate made of polar materials

We present a theoretical study of the electron- surface phonon interaction in mono-layer graphene (1LG) on polar substrates such as SiO2,HfO2,SiC and hexagonal BN. Thus we have used the eigen energies derived from the tight-binding Hamiltonian in mono-layer graphene. Our results indicate that the electron-surface phonon interaction depends on the polar substrate. Such polar substrates allow for the existence of polar optical phonons localized near the graphene-substrate interface which could be an important scattering source for graphene carriers through the long-range Fröhlich coupling. Likewise, we have investigated the effect of various dielectrics on the SO phonon-limited mobility, the SO phonon-limited resistivity, the SO phonon-limited conductivity and the scattering rate in single layer graphene by considering the effects of the SO optical phonon scattering arising from the polar substrates and by varying the temperature, the charge carrier density and the physical separation between graphene and interface of dielectric substrate.

Multi-Dielectric & Multi-Band operations on RF MEMS

Ever increasing demand for microwave operated applications has cultivated need for high-performance universal systems capable of working on multi-bands. This objective can be realized using Multi-Dielectrics in RF MEMS capacitive switch. In this study, we present a detailed analysis of the effect of various dielectrics on switch performance. The design consists of a capacitive switch and performance is analyzed by changing the dielectric layers beneath the switch. The results are obtained using three different dielectrics including Silicon nitride (7.6), Hafnium dioxide (25) and Titanium oxide (50). Testing of proposed switch yields high isolation (- 87.5 dB) and low insertion loss (- 0.1 dB at 50 GHz) which is substantially better than the conventional switches. The operating bandwidth of the proposed switch (DC to 95 GHz) makes it suitable for wide band microwave applications.

Correlation between volume effect and lifetime effect of solid dielectrics on nanosecond time scale

Theoretical analysis for the volume (V) effect on electric breakdown strength (EBD) and the operating field (Eop) effect on lifetime (NL) of solid dielectrics on a nanosecond time scale is presented in the perspective of the Weibull distribution. It is derived that the general formula for the volume effect is EBD=kV-1/m and the formula for the lifetime effect is NL=(EBD/Eop)m, where m is a parameter which is determined by the dielectric quality and influenced by the dielectric types. Besides that, it is found that the volume effect and the lifetime effect correlate with each other via m. By summarizing the experimental results, it is concluded that m is averaged to be 8 for polymers with a normal quality under short pulses and that m will be larger (or smaller) than 8 when polymers are with better (or poor) quality. It is suggested that m can be defined as a parameter to describe the dielectric's quality and m of 8 can be regarded as a criterion to choose polymers as insulation materials.

The effect of high-k gate dielectrics on device and circuit performances of a junctionless transistor

The impacts of high-k gate dielectric permittivity on the device and circuit performances of a double-gate junctionless transistor (DGJLT) are studied with the help of extensive device simulations. The results are compared with a conventional inversion mode double-gate metal oxide semiconductor field effect transistor (DG MOSFET) of same dimension. Drain induced barrier lowering, intrinsic gain $$(G_{m}R_{O})$$(GmRO), and unity gain cut-off frequency $$(f_{T})$$(fT) are degraded with an increase in gate dielectric permittivity $$(k)$$(k). The transconductance $$(G_{m})$$(Gm) and gate capacitance $$(C_{GG})$$(CGG) are slightly affected with increase in $$k$$k. The gain of CMOS single stage amplifier and delay of inverter are found to be decreasing and increasing, respectively, with increase in $$k$$k. In order to mitigate these short channel effects due to the high-k gate dielectrics, a hetero-gate-dielectric structure with symmetric double-gate junctionless transistor (HG-DGJLT) is studied. HG-DGJLT offers superior $$G_{m}, \, C_{GG}$$Gm,CGG and $$f_{T}$$fT compared to $$\hbox {SiO}_{2}$$SiO2-only and $$\hbox {HfO}_{2}$$HfO2-only DGJLT. However, intrinsic gain of HG-DGJLT is inferior to $$\hbox {SiO}_{2}$$SiO2-only and $$\hbox {HfO}_{2}$$HfO2-only DGJLT.

Dielectric substrate effect on the temperature-dependent electrical properties of pentacene films

Developing better contacts on dielectrics is one of the main challenges for pentacene-based transistor technology. This study investigates the effect of inorganic dielectrics on the temperature-dependent electronic property of pentacene films. It is found that the carrier mobility in the pentacene film deposited on a SiN x dielectric is higher than that in the pentacene film deposited on a SiO2 dielectric. However, the carrier density does not change substantially. The dependence of the carrier mobility upon temperature indicates the dominance of tunneling (hopping) at low (high) temperatures. The Hall-effect analysis by using the polaron theory revealed that the enhanced carrier mobility is due to the modified spacing between molecules in the pentacene layer.

Effect of thin gate dielectrics and gate materials on simulated device characteristics of 3D double gate JNT

In this paper a novel Silicon based three dimensional (3D) double-gate Junctionless Nanowire Transistor (JNT) of 20nm gate length is proposed. The device characteristics such as gate characteristics and drain characteristics are studied with the help of Sentaurus TCAD by using different gate materials such as Al, Ti, n+ Polysilicon, Au and using different ultra thin gate dielectrics such as SiO2, Si3N4 and HfO2. The effect of various work functions and dielectrics on the threshold voltage of the JNT is also analysed. From the TCAD simulation results it is observed that high-K material (HfO2) as gate dielectric shows better drain characteristics with respect to others. The JNT with Al as gate material gives better current characteristics with respect to others. It is also analysed that under flat-band condition the driving of drain current does not directly depend on the gate-oxide capacitance but depends upon the channel doping concentrations. Thus by choosing the proper gate material and gate dielectric combinations, the desired device characteristics could be obtained for JNT.

Effect of spacer dielectrics on performance characteristics of Ge-based tunneling field-effect transistors

In this study, we investigated the effects of dielectric materials for spacers on the performance characteristics of germanium (Ge)-based tunneling field-effect transistors (TFETs). Direct current (DC), radio frequency (RF), and switching performance characteristics were analyzed using various spacer dielectric materials including recent interlayer dielectric (ILD) oxides, silicon dioxide (SiO2), silicon nitride (Si3N4), and hafnium oxide (HfO2). Since spacer dielectrics affect the band bending in the source and drain regions caused by fringing fields, a Ge-based TFET having a low-κ spacer dielectric showed a high current drivability owing to its steep energy-band bending on the source side. At the same time, outstanding switching and RF performance characteristics were achieved by reducing parasitic capacitances when a low-κ spacer dielectric was employed. On this basis, a Ge-based TFET with a low-κ spacer dielectric was designed with a drain underlap for satisfactory control of the ambipolar behaviors and for optimization of RF performance characteristics. It was proven that the drain underlap suppressed ambipolar current characteristics and reduced gate capacitance by minimizing the electric field induced by the gate electrode on the drain-side channel without degradation of current drivability.

Mobility enhancement of SnO2nanowire transistors gated with a nanogranular SiO2solid electrolyte

Field-effect transistors (FETs) based on semiconducting nanowires are the most fundamental electronic elements for exploring charge transport as well as possible applications in functional nanoelectronics. Here, we report the effect of different gate dielectrics on the electrical performance of SnO2 nanowire FETs. By using solid-electrolytes with large electric-double-layer (EDL) capacitance as gate dielectrics, both low-voltage operation and high gating efficiency can be obtained. Electrical transport measurements indicate that the nanowire FETs gated by solid-electrolytes show improved electrical performances in terms of on-current, sub-threshold swing, and mobility, in comparison to those gated by traditional thermally grown dielectrics. The observed performance improvement is possibly due to the reduction of the contact-resistance and the Schottky barrier at the semiconductor/metal junctions.

Dielectric capping effects on binary and ternary topological insulator surface states

Using a density functional based electronic structure method, we study the effect of crystalline dielectrics on the metallic surface states of Bismuth- and chalcogen-based binary and ternary three dimensional topological insulator (TI) thin films. Crystalline quartz (SiO2) and boron nitride (BN) dielectrics were considered. Crystalline approximation to the amorphous quartz allows to study the effect of oxygen coverage or environmental effects on the surface states degradation which has gained attention recently in the experimental community. We considered both symmetric and asymmetric dielectric cappings to the sufaces of TI thin films. Our studies suggest that BN and quartz cappings have negligible effects on the Dirac cone surface states of both binary and ternary TIs, except in the case of an oxygen-terminated quartz surface. Dangling bond states of oxygens in oxygen-terminated quartz dominate the region close to Fermi level, thereby distorting the TI Dirac cone feature and burying the Dirac point in the quartz valence band region. Passivating the oxygen-terminated surface with atomic hydrogen removes these dangling bond states from the Fermi surface region, and consequently the clear Dirac cone is recovered. Our results are consistent with recent experimental studies of TI surface degradation in the presence of oxygen coverage.

Effect of Different High-K Dielectrics on the Pt Nanocrystal Formation Statistics (size, density and area coverage) for Flash Memory Application

ABSTRACTWe here present, metal nanocrystal (NC) formation statistics (size, density, occupancy or area coverage) on different high dielectric constant (high-K) materials which may be used as tunnel dielectric or intermetal dielectric in flash memory devices. Four important high-K materials viz. SiO2, Al2O3, HfO2 and Si3N4 are chosen for this purpose and the nanocrystal formation statistics has been found to be strongly dependent on dielectric. Among all the four dielectrics, smallest size nanocrystals with largest density are obtained on Al2O3 dielectric while on HfO2 bigger size nanocrystals are formed. This difference in nanocrystal size and density on different dielectrics is attributed to the different surface properties of these materials.

Quantum well mobility and the effect of gate dielectrics in remote doped InSb/AlxIn1 − xSb heterostructures

Low- and high-field magnetotransport measurements on 30 nm δ-doped InSb/AlInSb quantum wells with different doping densities are reported. Mobilities over the temperature range 2 to 290 K are described using the relaxation time approximation. Screening by electrons in the doping plane and the temperature variation of the Fermi wave vector and effective mass of the carriers are incorporated into the model. High quality, Shubnikov de Haas oscillations are observed in samples that exhibit single sub-band occupancy. However, higher density samples that show considerable parallel conductance with qualitatively poor ρxx(B) are shown to recover high quality Shubnikov de Haas oscillations by deposition of a surface gate with a SiO2 gate dielectric. We show that the incorporation of this gate dielectric significantly modifies the transport properties and results in an increased mobility over ungated structures with the same carrier density. These observations lead to further insight into the carrier scattering mechanisms present in these InSb/AlInSb structures.