Back-gate Effect Research Articles

Low-frequency noise in the Double SOI (DSOI) MOSFETs with back-gate control

In this paper, the impact of the back-gate voltage (Vb ) on the low-frequency (1/f) noise is evaluated for the 180 nm double silicon-on-insulator (DSOI) NMOS, fabricated with various thicknesses of first buried oxide (BOX1) layer (145/50 nm). Both positive and negative Vb increased the measured normalized drain current power spectral density (PSD) for more than ten-fold in DSOI standard devices with 145 nm BOX1, while the normalized PSD decreases with Vb going up in devices with 50 nm BOX1. By comparing with CNF+CMF model, interface trap density and the Coulomb scattering coefficient are extracted with the back-gate voltage applied. The interface trap density increases in standard devices for both positive and negative Vb , but decreases with increasing back-gate biasing from -10 V to 10 V in devices with 50 nm BOX1. The interface trap density shows a similar back-gate coupling effect with threshold voltage under the influence of different thickness of BOX1. The CNF and CMF noise variation under back-gate voltage can be explained by the significant fluctuation in drain current.

Nonlinear behaviors in back-gate effects of FDSOI MOSFETs at cryogenic temperatures

In this work, we systematically investigate the DC performance of fully depleted silicon-on-insulator (FD-SOI) MOSFETs at both room and cryogenic temperatures as low as 77 K. The influences of back-gate bias on normal and flip-well devices are measured and analyzed. Both types devices display non-linear behaviors when adjusting the back-gate voltage at cryogenic temperatures. Notably, the non-linear effects are more prominent in normal-well devices. The possible reasons are analyzed and verified by technology computer aided design simulation, suggesting that normal-well devices are more susceptible to the formation of depletion regions between the buried oxide layer and the well. This phenomenon disrupts the linearity of the back-gate effect. This research contributes to understanding and characterizing of the back-gate effects in cryogenic environments and holds potential for high-performance computing applications.

Batch production of centimeter-scale monolayer MoS2 with low nucleation by face-to-face metal precursor supply

Transition-metal dichalcogenides (TMDs) show great potential for next-generation semiconductor due to its atomic level thickness, tunable band gap and high carrier mobility. However, high-quality monolayer MoS2 (ML-MoS2) films require stringent growth conditions during preparation. Here, we report a face-to-face metal precursor supply approach during chemical vapor deposition (CVD) to batch production of uniform ML-MoS2 films. Mo foils provide a stable concentration of metal precursors leading to uniform film generation with low nucleation. Comprehensive characterization techniques, including spectroscopic, surface topography and atomic scale analysis confirm the centimeter-scale homogeneity and high crystallographic quality of the monolayer films. Back-gate field effect transistors (FET) fabricated by ML-MoS2 exhibit excellent electrical performance. This methodology provides a pathway for the growth of TMDs, which should promote their applications in high-performance electronics or other fields.

Impact of Dual-Gate Configuration on the Endurance of Ferroelectric Thin-Film Transistors With Nanosheet Polycrystalline-Silicon Channel Film

This work explores the characteristics of ferroelectric thin-film transistors (FeTFTs) utilizing an asymmetric dual-gate (DG) structure in both single-gate (SG) and DG operation modes. In the transfer characteristics, DG mode exhibits a memory window (MW) of 1.075 V, smaller than SG mode’s MW of 1.402 V, attributed to the back-gate bias effect causing a reduction in the device’s threshold voltage. However, DG mode demonstrates superior endurance characteristics with 106 cycles compared to SG mode’s 105 cycles. Additionally, the increase in erase pulse voltage (VERS) exacerbates the polycrystalline-silicon channel lattice damage of FeTFT, resulting in subthreshold swing (SS) degradation. Nevertheless, the extent of SS degradation from DG mode operation is significantly lower than that of SG mode, contributing to the superior endurance of DG mode. The elevation of program pulse voltage (VPRG) induces imprint and charge-trapping effects in the top-gate ferroelectric dielectric, leading to reduced endurance. Due to the use of SiO2 as the back-gate dielectric in FeTFT, DG mode exhibits lower impacts of charge-trapping effects from the top-gate ferroelectric dielectric layer, resulting in better endurance compared to SG mode. The asymmetric DG structure provides greater tolerance in the selection of VPRG and VERS.

A Novel Enhancement-Mode Gallium Nitride p-Channel Metal Insulator Semiconductor Field-Effect Transistor with a Buried Back Gate for Gallium Nitride Single-Chip Complementary Logic Circuits

In this work, a novel enhancement-mode GaN p-MISFET with a buried back gate (BBG) is proposed to improve the gate-to-channel modulation capability of a high drain current. By using the p-GaN/AlN/AlGaN/AlN double heterostructure, the buried 2DEG channel is tailored and connected to the top metal gate, which acts as a local back gate. Benefiting from the dual-gate structure (i.e., top metal gate and 2DEG BBG), the drain current of the p-MISFET is significantly improved from −2.1 (in the conv. device) to −9.1 mA/mm (in the BBG device). Moreover, the dual-gate design also bodes well for the gate to p-channel control; the subthreshold slope (SS) is substantially reduced from 148 to ~60 mV/dec, and such a low SS can be sustained for more than 3 decades. The back gate effect and the inherent hole compensation mechanism of the dual-gate structure are thoroughly studied by TCAD simulation, revealing their profound impact on enhancing the subthreshold and on-state characteristics in the BBG p-MISFET. Furthermore, the decent device performance of the proposed BBG p-MISFET is projected to the complementary logic inverters by mixed-mode simulation, showcasing excellent voltage transfer characteristics (VTCs) and dynamic switching behavior. The proposed BBG p-MISFET is promising for developing GaN-on-Si monolithically integrated complementary logic and power devices for high efficiency and compact GaN power IC.

An Improved Dual-Gate Compact Model for Carbon Nanotube Field Effect Transistors with a Back-Gate Effect and Circuit Implementation

Compared to single-gate CNTFET, dual-gate structures have better electrostatic control over nanowire conductive channels. However, currently, there is insufficient research on the back-gate effect in a compact model of dual-gate CNTFET. This paper presents an improved dual-gate carbon nanotube field effect transistor (CNTFET) compact model. The functional relationship between the back-gate voltage (Vbg) and threshold voltage (Vth) is derived. And a voltage reference regulation mechanism is adopted so that the back-gate effect can be accurately reflected in the DC transfer characteristics. The influence of gate voltage and drain voltage on transmission probability is analyzed. Meanwhile, the drain current is optimized by modifying the mobility equation. This compact model is built based on Verilog-A hardware language and supports the Hspice simulation tool. Within the supply voltage of 2 V, the simulation results of the proposed compact model are in good agreement with the measurement results. Finally, based on the compact model, an operational amplifier is designed to verify its correctness and feasibility in analog integrated circuits. When the power supply voltage is 1.8 V, and the load capacitance is 2 pF, the gain is 11.8 dB, and the unit-gain-bandwidth (UGB) is 214 kHz, which proves the efficiency of our compact model.

Full-Custom 90 nm CNTFET Process Design Kit: Characterization, Modeling, and Implementation

As the semiconductor industry enters the post-Moore era, the carbon nanotube field-effect transistor (CNTFET) has become a powerful substitute for silicon-based transistors beyond 5 nm process nodes due to its high mobility, low power consumption, and ultra-thin-body electrical advantages. Carbon-based transistor technology has made significant progress in device manufacture and preparation, but carbon-based process design kits (PDKs) that meet the standards of commercial design tools are still an important bottleneck hindering the development of carbon-based integrated circuits. For the first time, a complete full-custom 90 nm CNTFET PDK is proposed in this paper, which includes Pcells for transistors, resistors, and capacitors; a compact model; DRC/LVS/PEX rules; and a standard cell and timing library. It can support the entire design flow of analog, digital, and mixed-signal carbon-based integrated circuits. To achieve an accurate compact model, the back-gate effect of CNTFETs and the influence of gate/drain voltage on transport probability are analyzed. Then the theoretical formulas for mobility and channel current are established. The comparison of the simulation and test results of CNTFET characteristics proves the accuracy of the compact model. Using this PDK, combined with standard IC design tools and design flow, the circuit and layout of an operational amplifier, SRAM, and 8-bit counter are completed. The simulation results verify the correctness and effectiveness of the PDK, laying a solid foundation for the large-scale industrialization of carbon-based integrated circuits.

Potassium-doped nano graphene as an intermediate layer for graphene electronics

To suppress the intrinsic carrier density and increase the carrier mobility in graphene on a silicon dioxide (SiO2) substrate, potassium (K)-doped nano graphene was introduced as an intermediate layer between the graphene layer and SiO2 substrate. Back-gate type graphene field effect transistors with four terminal structures were fabricated, and their electrical properties were measured under vacuum. The results showed that the Dirac point shifted from +9.0 to −0.2 V after inserting the K-doped nano graphene. The results suggested that inserting the intermediate layer compensated for the intrinsic holes and achieved an electron doping of 2 × 1012 cm−2. The field-effect mobilities of electrons and holes also increased because the ionized K-atoms in the intermediate layer shielded the electric force from the negatively charged impurities in SiO2. The K density was estimated using x-ray photoelectron spectroscopy to be 1.49 × 1013 cm−2, and the C1s peak shifted by 0.2 eV, which confirms the upward modulation of the graphene Fermi level by the K-doped nano graphene intermediate layer. These results demonstrated the advantages of the intermediate layer on the carrier density and mobility in graphene.

Improved Subthreshold Characteristics by Back-Gate Coupling on Ferroelectric ETSOI FETs

In this work, extremely thin silicon-on-insulator field effective transistors (ETSOI FETs) are fabricated with an ultra-thin 3 nm ferroelectric (FE) hafnium zirconium oxides (Hf0.5Zr0.5O2) layer. Furthermore, the subthreshold characteristics of the devices with double gate modulation are investigated extensively. Contributing to the advantages of the back-gate voltage coupling effects, the minimum subthreshold swing (SS) value of a 40 nm ETSOI device could be adjusted from the initial 80.8–50 mV/dec, which shows ultra-steep SS characteristics. To illustrate this electrical character, a simple analytical model based on the transient Miller model is demonstrated. This work shows the feasibility of FE ETSOI FET for ultra-low-power applications with dynamic threshold adjustment.

Bias Dependence of Total Ionizing Dose Response in UTBB FD-SOI Transistors

The impact of continuous bias on the ultra-thin body and buried oxide fully-depleted silicon-on-insulator (UTBB FD-SOI) transistors during total ionizing dose (TID) irradiation is investigated by a device with the single transistor or multiple transistors in parallel. Experimental data of the single transistor shows that the TID bias effect is masked by TID response variation caused by process fluctuation between devices. While the device with multiple transistors in parallel still exhibits a similar TID bias effect as the traditional SOI transistor (TG > OFF > Ground > ON), the process fluctuations between devices are well controlled. Focusing on UTBB FD-SOI parallel transistors, by comparing the results of various bias conditions, the impacts of the drain, gate, and back-gate bias on the TID response of transistors are summarized in detail. Particularly, applying both positive and negative back-gate bias to transistors during TID radiation can obviously increase the TID damage of UTBB FD-SOI parallel transistors, which should be considered in the TID mitigation technique through dynamic back-gate bias. Combined with TCAD simulation, the generation process of oxide-trapped charges in buried oxide (BOX) under different biases is discussed. And, bias dependence of TID response is analyzed from three aspects: fraction of holes escaping initial recombination, holes capture cross section, and spatial distribution of oxide trapped charges. Finally, the TID mitigation calibration law of pMOSFETs is investigated by the empirical model of the back-gate radiation bias effect.

A 9.5nW, 0.55V Supply, CMOS Current Reference for Low Power Biomedical Applications

This brief proposes an ultra-low-power current reference in TSMC 180nm technology. Temperature compensation is achieved by taking the ratio of compensated voltage and an on-chip resistance. This design uses the concept of the back-gate effect of critical MOSFET to generate complementary to absolute temperature (CTAT) voltage. The circuit works from a supply voltage of 0.55V and is designed for a reference current of 5.6nA. Furthermore, a pseudo-differential amplifier (PD-AMP) helps realize low line regulation of 0.022%/V in the supply range of 0.55 to 1.9V. An average temperature coefficient (TC) of 256.07ppm/°C is achieved for mismatch and process variations in Monte-Carlo simulations for 1000 samples over a temperature range of −30°C to 70°C. The circuit consumes only 9.5nW of power (at room temperature and minimum supply voltage), making it suitable for ultra-low-power biomedical applications.

In-plane optical and electrical anisotropy in low-symmetry layered GeS microribbons

Layered group-IV monochalcogenides, including GeS, GeSe, SnS, and SnSe, garner attention because of their anisotropic structures and properties. Here, we report on the growth of GeS microribbons via chemical vapor transport (CVT), which affords each of them with a low-symmetry orthorhombic structure and anisotropic optical and electronic properties. The single-crystalline nature of the GeS microribbon, which has a typical thickness of ~30 nm, is confirmed. Polarized Raman spectra reveal angle-dependent intensities that are attributed to the anisotropic layered structure of GeS microribbons. The photoluminescence (PL) spectra reveal a peak at ~1.66 eV. The angle-dependent PL and anisotropic absorption spectroscopy results provide evidence for a distinct anisotropic optical transition near the energy band edges; this phenomenon is also predicted by our density functional theory (DFT)-based calculations. Strong in-plane direct-current transport anisotropy is observed under dark and white illumination by using back-gate cross-shaped field effect transistors (CSFETs) fabricated with the GeS microribbon; significant gate-tunable conductivity is also confirmed. The strong anisotropy is further confirmed by the DFT-calculated effective mass ratio. Our findings not only support the application of GeS microribbons in anisotropic photoelectronic transistors but also provide more possibilities for other functional device applications.

Back-gate effects on DC performance and carrier transport in 22 nm FDSOI technology down to cryogenic temperatures

This paper presents an in-depth DC characterization of a 22 nm FDSOI CMOS technology down to deep cryogenic temperature, i.e., 2.95 K. The impact of the back-gate voltage (Vback) on device performance, i.e., threshold voltage (VT) and carrier transport, is investigated over a wide temperature range. Moreover, semiclassical and quantum transports of two-dimensional carrier gas are investigated. The effective mobility (μeff) extracted from short devices at cryogenic temperatures is lower than actual mobility due to the presence of ballistic transport. The discontinuous ID–VG is found in both long and extremely short transistors, which is ascribed to the intersubband transition happening during the scattering event. Oscillatory ID–VG due to resonant tunneling manifests itself in short devices at cryogenic temperatures and depends on Vback. On the other hand, the worse subthreshold swing is found for short devices in the saturation regime and at cryogenic temperatures due to source-to-drain tunneling.

The low threshold-voltage shift with temperature and small subthreshold-slope in 28 nm UTBB FDSOI for 300 °C high-temperature application

Partially depleted silicon-on-insulator (PDSOI) MOSFETs are widely used in 225 °C high-temperature electronic system applications with integrated circuits. But the process node stays at 0.5 µm for a long time and no further breakthrough can be achieved. This paper reports the high-temperature characteristics of 28 nm ultra-thin body and box fully depleted SOI (FDSOI) CMOS transistors with low threshold voltage (LVT) structure. Experimental results demonstrate that V t shift changes with temperature as low as 0.59 mV °C−1, the subthreshold slope (SS) is 145.35 mV dec−1 at 300 °C, and the related parameters are optimized by 3.7 times and 2.2 times respectively compared with 0.13 µm PDSOI. Combined with theoretical analysis, it is proved that the ultra-body FDSOI has an LVT drift rate and better SS than 0.13 µm PDSOI at high temperature. The advantage of this performance is mainly due to the difference between VT and β VT coefficients related to the back gate effect. Under negative back-gate bias, the I on/l off ratio can be increased by two orders of magnitude without affecting V t shift changes with temperature, this proves that the FDSOI is capable of high-temperature applications above 300 °C. This paper provides substantial support for future high-temperature system integrated circuits from the micro-scale to the nano-scale.

Analytical Modeling of Short-Channel TMD TFET Considering Effect of Fringing Field and 2-D Junctions Depletion Regions

An analytical drain current model is developed for a short-channel, dual-gate, monolayer 2-D transition metal dichalcogenide (TMD), lateral tunnel field-effect transistor (TFET) by considering 2-D <inline-formula> <tex-math notation="LaTeX">${p}^{+}-{n}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${n}-{n}^{+}$ </tex-math></inline-formula> junction at source&#x2013;channel and channel&#x2013;drain junction, respectively. This work includes the effect of both front- and back-gate dielectric fringing field effects and 2-D source and drain depletion charges. A unified piecewise surface potential model is developed by capturing the fringing field effects in the channel and 2-D junction behavior at the source&#x2013;channel and channel&#x2013;drain junction by ensuring continuity of electric field at the junction regions. A tangent-line approximation method is employed for accurate numerical evaluation of the tunneling current. The proposed model is validated with simulation results obtained using nonequilibrium Green&#x2019;s function (NEGF)-based simulator for different 2-D layered materials and a close agreement is observed. The veracity of the proposed model is tested with data in reported studies for different bias conditions and excellent matching is observed. The applicability of the model is demonstrated for any 2-D layered material-based TFET from ultrashort channel to a channel length of 50 nm. The proposed model will be extremely useful for further exploration of 2-D TMD material TFET-based very large-scale integration (VLSI) circuits.

Back-gate bias effect on the linearity of pocket doped FDSOI MOSFET

In this article, we investigate the feasibility of enhancing the linearity Figures of Merit (FoMs) by introducing pocket implant in the source/drain regions of the FDSOI MOSFET with ground plane (GP) under the influence of back-gate bias (VB) effect. The current investigations are carried out using a well calibrated industry standard simulation tool Silvaco ATLAS. The proposed device architecture shows reduction in peak electric field, improvement in effective mobility (μeff), subthreshold slope (SS), threshold voltage (VTH) & off-state current (IOFF) by rearranging the accumulated charges that can mitigate impact ionization. The improvement in these parameters leads to enhanced the fundamental transconductance term (gm) and in turn boosts the linearity, which can make it essential for RF/wireless IC designs. An investigation is performed to figure out the non-linear behaviour of proposed FDSOI MOSFET with pockets design by simulating the DC characteristics. The vital FoMs such as higher order transconductance coefficients, intermodulation distortion (IM) and input intercept point (IIP) are explicitly analysed along with the impact of VB.

Realization of ppb-level acetone detection using noble metals (Au, Pd, Pt) nanoparticles loaded GO FET sensors with simultaneous back-gate effect

In the current study, graphene oxide (GO), uniformly loaded with different noble metal nanoparticles (Au, Pd and Pt) were synthesized by spray coating technique and implemented in field effect transistor (FET) sensors. The morphology, structure, composition and electronic properties of the synthesized materials were characterized. The sensing results indicated that the incorporation of noble metals can greatly enhance the VOC sensing properties of a few layers of GO by using their chemical and electrical sensitization effect. At optimized gate potential, GO FET exhibited outstanding sensing properties at low operating temperature i.e. 50 °C. Specifically, the FET sensor based on Pd loaded GO exhibited the highest response, quickest response/recovery (37 s/91 s) characteristics, best selectivity and low operating temperature towards low concentration of acetone. Almost five times higher sensitivity towards acetone (400 ppb) was achieved in Pd/GO as compared to the pure GO channel nanoparticles under a suitable back gate bias.

Design and verification of a high performance analog switch circuit

A double-pole double-throw analog switch circuit structure with low power consumption, low on-resistance and capable of transmitting negative signals is designed in this paper, which has been developed in 0.18 μm BCD technology. The analog switch circuit is providing about 5 V high swing signal transmission for 2.7–5 V supply voltage in the temperature range of − 40 to 85 °C. The shortcomings of traditional analog switch structure are large on-resistance, large power consumption, etc. In this paper, the charge pump structure of the gate voltage bootstrap switch is designed to overcome the backgate effect, to control the turn-on and turn-off of each switching MOS transistor. A dynamic comparator structure is used to enhance the signal transmission capability, so that the analog switch can transmit negative signal. The measurement results show that under the voltage of 2.7–5 V, the overall designed circuit consumes 92 μW. The on-resistance of the analog switch is 3.9 Ω, and the leakage current is 12 nA. The analog switch has a good signal transmission and shutdown capabilities while occupying an area of 0.67 mm2.

Monolithic Integrated AlGaN/GaN Power Converter Topologies on High‐Voltage AlN/GaN Superlattice Buffer

Semiconductor Superlattices The picture shows a monolithic power converter, fabricated in a lateral AlGaN/GaN-on-Si process on an improved AlN/GaN super-lattice buffer epitaxy. The super-lattice reduces vertical leakage and back-gating effects compared to step-graded buffers. This improved integration technology allows 98.8% efficient dc-dc conversion on a single chip. More details can be found in article number 2000404 by Stefan Moench and co-workers.

GaN Integrated Bridge Circuits on Bulk Silicon Substrate: Issues and Proposed Solution

A discrete GaN power transistor’s substrate is typically connected to its source electrode. However, on the GaN-on-Si power IC platform, the high-side transistor (HS-transistor) and low-side transistor (LS-transistor) share a common substrate that cannot be simultaneously connected to both source electrodes of the two transistors. Thus, the termination of the common substrate remains an undecided issue. In this work, comprehensive TCAD simulations are exploited to reveal the influences of various substrate termination schemes. It is found the common substrate inevitably leads to severe degradation in the dynamic ${R} _{\mathrm{ ON}}$ due to back-gating effects. The mechanisms for the degradations vary with the substrate termination scheme, and will be discussed in detail. To address these issues, we propose a new GaN power IC platform on an engineered bulk silicon substrate, and study the new platform with TCAD simulations. The proposed platform provides a local electrical substrate (a p+ island) for each GaN power transistor. The source electrode of each GaN transistor is connected to its local electrical substrate, while all devices share a common mechanical substrate. The junctions between the local substrates and the underlying n-layer provide an effective isolation between GaN transistors. The back-gating effects are completely suppressed for the GaN integrated bridge circuit.