Back-gate bias effect on the linearity of pocket doped FDSOI MOSFET

Abstract

In this article, we investigate the feasibility of enhancing the linearity Figures of Merit (FoMs) by introducing pocket implant in the source/drain regions of the FDSOI MOSFET with ground plane (GP) under the influence of back-gate bias (VB) effect. The current investigations are carried out using a well calibrated industry standard simulation tool Silvaco ATLAS. The proposed device architecture shows reduction in peak electric field, improvement in effective mobility (μeff), subthreshold slope (SS), threshold voltage (VTH) & off-state current (IOFF) by rearranging the accumulated charges that can mitigate impact ionization. The improvement in these parameters leads to enhanced the fundamental transconductance term (gm) and in turn boosts the linearity, which can make it essential for RF/wireless IC designs. An investigation is performed to figure out the non-linear behaviour of proposed FDSOI MOSFET with pockets design by simulating the DC characteristics. The vital FoMs such as higher order transconductance coefficients, intermodulation distortion (IM) and input intercept point (IIP) are explicitly analysed along with the impact of VB.