Bias Dependence of Total Ionizing Dose Response in UTBB FD-SOI Transistors

Abstract

The impact of continuous bias on the ultra-thin body and buried oxide fully-depleted silicon-on-insulator (UTBB FD-SOI) transistors during total ionizing dose (TID) irradiation is investigated by a device with the single transistor or multiple transistors in parallel. Experimental data of the single transistor shows that the TID bias effect is masked by TID response variation caused by process fluctuation between devices. While the device with multiple transistors in parallel still exhibits a similar TID bias effect as the traditional SOI transistor (TG > OFF > Ground > ON), the process fluctuations between devices are well controlled. Focusing on UTBB FD-SOI parallel transistors, by comparing the results of various bias conditions, the impacts of the drain, gate, and back-gate bias on the TID response of transistors are summarized in detail. Particularly, applying both positive and negative back-gate bias to transistors during TID radiation can obviously increase the TID damage of UTBB FD-SOI parallel transistors, which should be considered in the TID mitigation technique through dynamic back-gate bias. Combined with TCAD simulation, the generation process of oxide-trapped charges in buried oxide (BOX) under different biases is discussed. And, bias dependence of TID response is analyzed from three aspects: fraction of holes escaping initial recombination, holes capture cross section, and spatial distribution of oxide trapped charges. Finally, the TID mitigation calibration law of pMOSFETs is investigated by the empirical model of the back-gate radiation bias effect.