ECL Gate Delay Research Articles

Silicon Germanium Heterojunction Bipolar Transistor for Digital Application

Bipolar transistor performances can be characterized by figures of merit such as cutoff frequency, maximum frequency of oscillation and ECL gate delay. We studied the required figures of merit for digital application and the effects of lateral and vertical scaling to the figures of merit of SiGe HBT. With lateral scaling, the width of emitter finger is scaled down from 0.25 to 0.12 ?m while with the vertical scaling, the base width is scaled down to reduce the base delay. We also observed the effects of Ge profile and Ge fraction to the devices performances. Bipole3 5.3.1G is used to help us in the study. We found that high frequency cutoff and maximum frequency of oscillation as well as low ECL gate delay are all important for digital applications. Scaling down the emitter finger width enhanced the maximum frequency of oscillation and reduced ECL gate delay significantly while scaling down the base width increased the cutoff frequency and current gain. DOI: http://dx.doi.org/10.11591/telkomnika.v10i3.609

A High-Performance SiGe HBT/BiCMOS Technology

A high-performance SiGe HBT/BiCMOS technology is reviewed. A nano-meter scaling of epitaxial SiGe base layer is an effective to improve cutoff frequency. Non-self-aligned structure and self-aligned structure in SiGe HBTs are compared in terms of their process flows and characteristics. An ECL gate delay of 4.9 psec is achieved by the high-yield self-aligned SiGe HBTs with a maximum oscillation frequency of 183 GHz. Without performance degradation the SiGe HBT and advanced CMOS technology are integrated with high-performance passive elements for mixed signal system-on-a-chips.

SiGe HBT/BiCMOS Technologies and their Applications to Communication ICs/LSIs

ABSTRACTSelf-aligned ultra-high-speed SiGe HBTs were developed by using selective epitaxial growth (SEG) technology. The use of HCl-free SEG, incorporation of C, and optimization of doping profiles significantly improves the performance of the HBT, producing a transistor with a high cutoff frequency of 170 GHz and a maximum oscillation frequency of 204 GHz, for a minimum ECL gate delay time of 4.8 ps. This is applied in a 16:1 MUX with a maximum clock rate of 57 GHz. A 0.13-μm SiGe BiCMOS technology is also realized without any degradation of CMOS due to the high stability of SiGe HBTs. Furthermore, the structure of SiGe HBT is optimized for an emitter scaled down towards 100 nm, mainly through the use of a funnel-shaped emitter electrode to reduce both emitter and base resistances. High-speed operation of a static frequency divider demonstrates the advantage of SiGe HBTs for ultra-high-speed communications systems.

3.48 ps ECL ring oscillator using over-300 GHz f T / f max InP DHBTs

An ECL gate delay of 3.48 ps/stage in a 19-stage conventional ring oscillator fabricated in an over-300 GHz fT/fmax InP DHBT technology has been demonstrated. This is the first report (to the authors' knowledge) of sub-4 ps ECL gate delay. Large collector current density contributes to the very short gate delay.

A 0.2-μm 180-GHz-f/sub max/ 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications

A technology for combining 0.2-/spl mu/m self-aligned selective-epitaxial-growth (SEG) SiGe heterojunction bipolar transistors (HBTs) with CMOS transistors and high-quality passive elements has been developed for use in microwave wireless and optical communication systems. The technology has been applied to fabricate devices on a 200-mm SOI wafer based on a high-resistivity substrate (SOI/HRS). The fabrication process is almost completely compatible with the existing 0.2-/spl mu/m bipolar-CMOS process because of the essential similarity of the two processes. SiGe HBTs with shallow-trench isolations (STIs) and deep-trench isolations (DTIs) and Ti-salicide electrodes exhibited high-frequency and high-speed capabilities with an f/sub max/ of 180 GHz and an ECL-gate delay of 6.7 ps, along with good controllability and reliability and high yield. A high-breakdown-voltage HBT that could produce large output swings for the interface circuit was successfully added. CMOS devices (with gate lengths of 0.25 /spl mu/m for nMOS and 0.3 /spl mu/m for pMOS) exhibited excellent subthreshold slopes. Poly-Si resistors with a quasi-layer-by-layer structure had a low temperature coefficient. Varactors were constructed from the collector-base junctions of the SiGe HBTs. MIM capacitors were formed between the first and second metal layers by using plasma SiO/sub 2/ as an insulator. High-Q octagonal spiral inductors were fabricated by using a 3-/spl mu/m thick fourth metal layer.

A 0.2-μm self-aligned selective-epitaxial-growth SiGe HBT featuring 107-GHz f/sub max/ and 6.7-ps ECL

A 0.2-/spl mu/m self-aligned selective-epitaxial-growth (SEG) SiGe heterojunction bipolar transistor (HBT), with shallow-trench and dual-deep-trench isolations and Ti-salicide electrodes, has been developed. The 0.6-/spl mu/m-wide Si-cap/SiGe-base multilayer was selectively grown by UHV/CVD. The process, except the SEG, is almost completely compatible with well-established bipolar-CMOS technology and the SiGe HBTs were fabricated on a 200-mm wafer line. The SiGe HBTs have demonstrated a peak cutoff frequency of 90 GHz, a peak maximum oscillation frequency of 107 GHz, and an ECL gate delay time of 6.7 ps. Four-level interconnects, including MIM capacitors and high-Q inductors, were formed by chemical mechanical polishing.

A selective-epitaxial-growth SiGe-base HBT with SMI electrodes featuring 9.3-ps ECL-gate delay

An ultra-high-speed selective-epitaxial-growth SiGe-base heterojunction bipolar transistor (HBT) with self-aligned stacked metal/in-situ doped poly-Si (IDP) (referred to as SMI) electrodes is developed. A 0.5-/spl mu/m-wide SiGe base self-aligned to the 0.1-/spl mu/m-wide emitter was selectively grown by using a UHV/CVD system. This self-aligned structure effectively reduces collector capacitance. In SMI technology, a tungsten film is selectively stacked on all poly-Si electrodes (base, emitter, and collector) in a self-aligned manner by using selective deposition without any heat treatment. So this technology does not cause unwanted diffusion of the base dopants and keeps a shallow intrinsic base profile. SMI technology can therefore provide low parasitic resistances and is well-suited to an SiGe-base HBT. A 2-/spl mu/m-wide BPSG/SiO/sub 2/ refilled trench was introduced in order to reduce the substrate capacitance. The low dielectric constant of BPSG/SiO/sub 2/ and the wide trench are very effective in reducing the sidewall element of substrate capacitance. This technology makes it possible to obtain ultra-high-speed operation with a 9.3-ps-gate-delay emitter-coupled-logic (ECL) circuit.

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 /spl mu/m CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 /spl mu/A is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 /spl mu/W 1 GHz prescaler circuit is demonstrated using this technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications

A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 /spl mu/m design rules (0.5 /spl mu/m as one nesting tolerance) has achieved f/sub l/ and f/sub max/ for npn bipolar (A/sub e/=1/spl times/2 /spl mu/m/sup 2/) of 23 GHz and 24 GHz at V/sub ce/=3 V, respectively, with BV/sub ceospl ges/5.5 volts, and /spl beta/V/sub A/ product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (A/sub e/=1/spl times/2 /spl mu/m/sup 2/; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 /spl Aring/, L/sub eff/=0.6 /spl mu/m; V/sub th,nch/=0.45 V; V/sub th,pch/=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 /spl mu/m; gate L/sub eff/=0.7 /spl mu/m) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Sub-20 ps high-speed ECL bipolar transistor with low parasitic architecture

Reducing parasitic capacitance and resistance is an effective means of both improving ECL gate delay and increasing f/sub T/ values. In this paper, we demonstrate a device with sub-20 ps t/sub pd/ values even at f/sub T/=23 GHz, a performance which has been achieved by implementing a number of techniques. These include 1) low-stress deep- and shallow-trench isolation to reduce C/sub CB/, 2) a low-concentration collector design to reduce C/sub CB/, 3) NiSi-salicided base and emitter electrodes to reduce R/sub B/, and 4) a shallow base formed by double diffusion technology for relatively high f/sub T/ with a low-concentration collector design. The low-concentration collector design gives the device a high breakdown voltage of 6.2 V. >

Very-high-speed silicon bipolar transistors with in-situ doped polysilicon emitter and rapid vapor-phase doping base

We present a detailed study of the performance of very-high-speed silicon bipolar transistors with ultra-shallow junctions formed by thermal diffusion. Devices are fabricated with double-polysilicon self-aligned bipolar technology with U-groove isolation on directly bonded SOI wafers to reduce the parasitic capacitances. Very thin and low resistivity bases are obtained by rapid vapor-phase doping (RVD), which is a vapor diffusion technique using a source gas of B/sub 2/H/sub 6/. Very shallow emitters are formed by in-situ phosphorus doped polysilicon (IDP) emitter technology with rapid thermal annealing (RTA). In IDP emitter technology, the emitters are formed by diffusion from the in-situ phosphorus doped amorphous silicon layer. Fabricated transistors are found to have ideal I-V characteristics, large current gain and low emitter resistance for a small emitter. Furthermore, a minimum ECL gate delay time of 15 ps is achieved using these key techniques. Analyses of the high performance using circuit and device simulations indicate that the most effective delay components of an ECL gate are cut-off frequency and base resistance. A high cut-off frequency is achieved by reducing the base width and active collector region. In this study, RVD is used to achieve both high cut-off frequency and low base resistance at the same time. >

A novel high-speed silicon bipolar transistor utilizing SEG and CLSEG

The concept and fabrication results are presented for a novel high-speed silicon bipolar transistor structure using selective epitaxy (SEG) and confined lateral growth (CLSEG) to form a double self-aligned single crystal contacted device. It provides significant improvements in the parasitics C/sub cb/ and C/sub cs/, and in the ECL gate delay.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

SiGe drift base bipolar transistor with self-aligned selective CVD-tungsten electrodes

A new device and process technology is developed for high-speed SiGe epitaxial base transistors. A 60-nm SiGe epitaxial base and the selectively ion-implanted collector (SIC) structure enhance the cutoff frequency to about 40 GHz. Base resistance is minimized to 165 /spl Omega/ (emitter area: 0.2/spl times/3 /spl mu/m/sup 2/), and an f/sub MAX/ of 37.1 GHz is achieved by employing 0.2-/spl mu/m EB lithography for the emitter window, selective CVD tungsten for the base electrode and a self-aligned oxide side wall for the emitter-to-base separation. Circuit simulations predict that this device could reduce the ECL gate delay to below 20 ps.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 6 GHz 68 mW BiCMOS phase-locked loop

The design of a 6 GHz fully monolithic phase-locked loop fabricated in a 1 /spl mu/m, 20 GHz BiCMOS technology is described. The circuit incorporates a voltage-controlled oscillator that senses and combines the transitions in a ring oscillator to achieve a period equal to two ECL gate delays. A mixer topology is also used that exhibits full symmetry with respect to its inputs and operates with supply voltages as low as 1.5 V. Dissipating 60 mW from a 2 V supply, the circuit has a tracking range of 300 MHz, an rms jitter of 3.1 ps, and phase noise of -75 dBc/Hz at 1 kHz offset. >

An ultra-high-speed ECL-BiCMOS technology with silicon fillet self-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 /spl mu/m gate and 50 ps on 0.6 /spl mu/m gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 /spl mu/m emitter ring oscillators with collector current density of 40 kA/cm/sup 2/. A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology. >

Integration of a double-polysilicon emitter-base self-aligned bipolar transistor into a 0.5- mu m BiCMOS technology for fast 4-Mb SRAM's

The single-polysilicon non-self-aligned bipolar transistor in a 0.5- mu m BiCMOS technology has been converted into a double-polysilicon emitter-base self-aligned bipolar transistor with little increase in process complexity. Improved bipolar performance in the form of smaller base resistance and base-collector capacitance, larger knee current, higher peak cutoff frequency, and shorter ECL gate delay has been demonstrated. This technology will prove useful in meeting the requirements for higher performance in fast, high-density, SRAM circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications. II. Circuit performance issues

For pt.I see ibid., vol.40, no.3, p.525-41 (1993). The circuit performance issues associated with optimizing epitaxial Si- and SiGe-base bipolar technology for the liquid-nitrogen temperature environment are examined in detail. It is conclusively demonstrated that the notion that silicon-based bipolar circuits perform poorly at low temperatures is untrue. Transistor frequency response is examined both theoretically and experimentally, with particular attention given to the differences between SiGe and Si devices as a function of temperature. ECL and NTL ring oscillator circuits were fabricated for each of the four profiles described in pt.I. The minimum ECL gate delay for a SiGe base is essentially unchanged from its room-temperature value. ASTAP models were used to explore circuit operation under typical wire loading. The results indicate that epitaxial-base bipolar technology offers significant leverage for future cryogenic applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

First demonstration of 60 GHz- f T , GaInP/GaAs HBT IC technology with 28 ps ECL gate delay

A fully integrated GaInP/GaAs HBT IC process with Schottky diodes, nichrome resistors, MIM capacitors and air-bridge inductors is presented. The HBTs have an fT and fmax of 60 and 45 GHz, respectively. Unloaded ECL gate delays of 28 ps are obtained from ring oscillator measurements. A divide-by-eight prescaler circuit clocks at 12.5 GHz.

Profile study of a graded epitaxial stack and its impact on high performance bipolar devices

Advanced MOSAIC V technology uses a graded epitaxial stack of 0-9μm n epitaxial layer grown on an n + buried layer which has been implanted into an inirinsic epitaxial layer. A study of the intrinsic epitaxial layer profile is critical for reducing the collector substrate (Ccs) capacitance which adversely affects the ECL gate delay. The importance of the intrinsic epitaxial layer profile for the performance of trench isolated high performance ASIC bipolar transistors is considered.

Partial-SOI isolation structure for reduced bipolar transistor parasitics

A bipolar isolation structure with the capability of significantly reducing collector-base capacitance and base resistance is presented. Partial SOI, with SOI surrounding the collector opening, can be used to reduce the collector window width in combination with any emitter-base self-aligned bipolar device structure, and in particular for device structures that feature sublithographic emitter width. Near-ideal transistor Gummel characteristics and a minimum ECL gate delay of 24 ps have been achieved with a nonoptimized lateral device layout, and simulations suggest that sub-20-ps delay at reduced switch current will be possible by using the optimized partial-SOI isolation structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>