Integration of a double-polysilicon emitter-base self-aligned bipolar transistor into a 0.5- mu m BiCMOS technology for fast 4-Mb SRAM's

Abstract

The single-polysilicon non-self-aligned bipolar transistor in a 0.5- mu m BiCMOS technology has been converted into a double-polysilicon emitter-base self-aligned bipolar transistor with little increase in process complexity. Improved bipolar performance in the form of smaller base resistance and base-collector capacitance, larger knee current, higher peak cutoff frequency, and shorter ECL gate delay has been demonstrated. This technology will prove useful in meeting the requirements for higher performance in fast, high-density, SRAM circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>