Abstract
A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 /spl mu/m design rules (0.5 /spl mu/m as one nesting tolerance) has achieved f/sub l/ and f/sub max/ for npn bipolar (A/sub e/=1/spl times/2 /spl mu/m/sup 2/) of 23 GHz and 24 GHz at V/sub ce/=3 V, respectively, with BV/sub ceospl ges/5.5 volts, and /spl beta/V/sub A/ product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (A/sub e/=1/spl times/2 /spl mu/m/sup 2/; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 /spl Aring/, L/sub eff/=0.6 /spl mu/m; V/sub th,nch/=0.45 V; V/sub th,pch/=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 /spl mu/m; gate L/sub eff/=0.7 /spl mu/m) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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