An advanced 0.8 mu m complementary BiCMOS technology for ultra-high speed circuit performance

Abstract

An 0.8- mu m fully complementary BiCMOS (CBiCMOS) process has been developed which offers superior drive capability and low-voltage performance compared to standard BiCMOS technologies. The CBiCMOS process was developed by the successful integration of a high-performance, poly emitter vertical PNP (F/sub t/=17 GHz, emitter coupled logic gate delay=65 ps) and CMOS transistors (CMOS gate delay=68 ps). A CBiCMOS push-pull ring oscillator has been fabricated with a gate delay of 250 ps for a 1-pF load; this is believed to be the fastest loaded ring gate delay ever reported for gate lengths down to 0.6 mu m. This CBiCMOS technology is expected to play an important role in the development of future generations of high-speed memories (i.e., 4-Mbit emitter coupled logic I/O SRAMs and beyond) which will require novel process technologies to avoid the deleterious effects of reduced voltage operation. >