Evaluation of high-performance SOI complementary BiCMOS devices by using test structures

Y Tamaki,C Kamada,E Yoshida,K Tsuji,Y Chida,T Iwasaki,T Tomatsuri,J Kumazawa

doi:10.1109/icmts.2001.928670

Evaluation of high-performance SOI complementary BiCMOS devices by using test structures

Y Tamaki, C Kamada + Show 6 more

https://doi.org/10.1109/icmts.2001.928670

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Publication Date: Mar 19, 2001

Citations: 5

Affiliation: Hitachi (Japan)

#Complementary BiCMOS Process #Complementary BiCMOS + Show 8 more

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Abstract

We used new test structures to evaluate the performance of complementary bipolar transistors fabricated on a SOI substrate by a new 0.35 /spl mu/m complementary BiCMOS process. The fabricated NPN transistors have a cut-off frequency (f/sub T/) of 10.5 GHz at a C-E breakdown voltage of 19.5 V and the PNP transistors have f/sub T/ of 6.0 GHz at 17.8 V. The test structure measurement showed that the high performance is due to the new isolation structure of the BiCMOS transistor and its layout.

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