Dynamic Amplifier Research Articles

A PVT-Robust AFE-Embedded Error-Feedback Noise-Shaping SAR ADC With Chopper-Based Passive High-Pass IIR Filtering for Direct Neural Recording.

This paper presents a PVT-robust error-feedback (EF) noise-shaping SAR (NS-SAR) ADC for direct neural-signal recording. For closed-loop bidirectional neural interfaces enabling the next generation neurological devices, a wide-dynamic-range neural recording circuit is required to accommodate stimulation artifacts. A recording structure using an NS-SAR ADC can be a good candidate because the high resolution and wide dynamic range can be obtained with a low oversampling ratio and power consumption. However, NS-SAR ADCs require an additional gain stage to obtain a well-shaped noise transfer function (NTF), and a dynamic amplifier is often used as the gain stage to minimize power overhead at the cost of vulnerability to PVT variations. To overcome this limitation, the proposed work reutilizes the capacitive-feedback amplifier, which is the analog front-end of the neural recording circuit, as a PVT-robust gain stage to achieve a reliable NS performance. In addition, a new chopper-based implementation of a passive high-pass IIR filter is proposed, achieving an improved NTF compared to prior EF NS-SAR ADCs. Fabricated in a 180-nm CMOS process, the proposed NS-SAR ADC consumes 4.3-μW power and achieves a signal-to-noise-and-distortion ratio (SNDR) of 71.7 dB and 82.7 dB for a bandwidth of 5 kHz and 300 Hz, resulting in a Schreier figure of merit (FOM) of 162.4 dB and 162.1 dB, respectively. Direct neural recording using the proposed NS-SAR ADC is demonstrated successfully in vivo, and also its tolerance against stimulation artifacts is validated in vitro.

Nonlinear Dynamic Analysis of Bistable Piezoelectric Energy Harvester with a New-Type Dynamic Amplifier.

A distributed parametric mathematical model of a new-type dynamic magnifier for a bistable cantilever piezoelectric energy harvester is proposed by using the generalized Hamilton principle. The new-type dynamic magnifier consists of a two-spring-mass system, one is placed between the fixed end of the piezoelectric beam and the L-shaped frame, and the other is placed between the L-shaped frame and the base structure. We used the harmonic balance method to obtain the analytical expressions for the steady-state displacement, steady-state output voltage, and power amplitude of the system. The effect of the distance between the magnets, the spring stiffness ratio and mass ratio of the two dynamic magnifiers, and the load resistance on the performance of the harvester is investigated. Analytical results show that compared with the bistable piezoelectric energy harvester with a typical spring-mass dynamic magnifier, the proposed new-type energy harvester system with a two-spring-mass dynamic magnifier can provide higher output power over a broader frequency band, and increasing the mass ratio of the magnifier tip mass to the tip magnet can significantly increase the output power of the BPEH + TDM system. Properly choosing the stiffness ratio of the two dynamic amplifiers can obviously improve the harvested power of the piezoelectric energy harvester at a low excitation level.

A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier

This article presents a single-channel 3.3-GS/s 6-b pipelined analog-to-digital converter (ADC), which features a post-amplification residue generation (PARG) scheme, linearized dynamic amplifier (DA), and on-chip calibration to achieve a high speed, low power, and compact prototype. The PARG scheme allows the quantization and amplification to run in parallel for a fast pipelining operation. The 6-b ADC consists of six pipelined stages with six comparators and five amplifiers in total. Such a small number of hardware reduce the overhead from the calibration and enable fully on-chip implementation. By further sharing the calibration hardware between the offset and gain calibration, the ADC with on-chip calibration only occupies 0.0166 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 28-nm CMOS. With a linearized DA for the residue amplification, the ADC achieves 34-dB signal-to-noise and distortion ratio (SNDR) with a Nyquist input with 3.3 GS/s, consuming 5.5 mW and yielding a 40.02-fJ/conversion-step Walden figure of merit (FoM).

A 0.0012 mm2 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

This paper presents a high-speed successive approximation register (SAR) analog-to-digital converter (ADC) that takes advantage of both asynchronous SAR ADC and loop-unrolled (LU) SAR ADC. By utilizing the output of the dynamic amplifier (DA) to generate an asynchronous clock, the reset time for the DA can be hidden behind the comparator latching time. Dedicated latches for each digital-to-analog converter (DAC) element eliminate the need for DAC switching logic. The proposed inverter-inserted three-stage comparator significantly reduces the input-referred offset of the comparator. The prototype 6-bit 700 MS/s SAR ADC was implemented in a 28 nm CMOS process and has a small 0.0012 mm2 area. The measured peak DNL and INL without any mismatch calibration were 0.33 and 0.27 LSB, respectively. With Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) were 34.07 and 47.52 dB, respectively. The power consumption was 1 mW under a supply voltage of 1.0 V, leading to a Walden figure of merit (FoM) of 34.6 fJ/conversion-step at 700 MS/s.

Dynamic Characteristics Analysis of Tri-Stable Cantilever Piezoelectric Energy Harvester with a Novel-type Dynamic Amplifier

In this paper, a non-linear tri-stable piezoelectric cantilever energy harvester with a novel-type dynamic magnifier was proposed to achieve more effective broadband energy harvesting under low-level ambient excitations. According to the generalized Hamilton principle, a mathematical distributed parameter model of the piezoelectric energy harvester was proposed. The novel-type dynamic magnifier is a system consisting of two spring masses, one placed between the fixed end of the piezoelectric beam and the L-shaped frame, and the other, between the L-shaped frame and the base. The harmonic balance method was adopted to work out the analytical expressions of the steady-state displacement, steady-state output voltage and power amplitude of the energy harvester system. The effects of the distance between the magnets, the spring stiffness of the dynamic magnifier, and the load resistance on the performance of the system were also investigated. The results show that different from that of the conventional tri-stable piezoelectric energy harvester, the frequency response curve of the proposed novel-type energy harvester system with a two-spring-mass dynamic magnifier exhibits two peaks as a result of the interactions of the coupled elastic system, where the left peak stands for the resonant value of the tri-stable piezoelectric energy harvester, while the right one the resonant value of the dynamic magnifier. It is able to achieve higher output power over a broader frequency band under low-level environmental excitations, and the harvested power can be significantly strengthened if the mass and stiffness of the dynamic magnifier are selected properly.

A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier

A pipelined SAR ADC is proposed to achieve faster conversion by employing residue conversion and partial bit conversion in parallel to lessen timing constraints. Additionally, a varactor-based dynamic amplifier is adopted to improve linearity for a 10-b accuracy. The single-channel ADC achieves 1 GS/s with a peak SNDR 41.37 dB at a Nyquist input and consumes 9.4 mW.

A 1.55-mW 2-GHz ERBW 7-b 800-MS/s Pipelined SAR ADC in 28-nm CMOS Using a 7T Dynamic Residue Amplifier

This letter presents a 3-stage pipelined successive-approximation-resister (SAR) analog-to-digital converter (ADC) using a seven transistor-dynamic residue amplifier (7T-DA) for kickback noise cancelation. Thanks to the pipeline structure, the input capacitance is only 16 fF, achieving an effective resolution bandwidth (ERBW) of 2 GHz. The gain sensitivity to the temperature of the dynamic amplifier is reduced by an on-chip low-dropout voltage regulator (LDO) and a pulse generator. Fabricated in the 28-nm CMOS process, the prototype ADC running at 800 MS/s achieves a peak SNDR of 42.7 dB and SFDR of 52.0 dB at Nyquist input. It also achieves SNDR of 38.9 dB and SFDR of 49.9 dB at a 2-GHz input. The total power consumption of ADC is 1.55 mW, which corresponds to the Waldon figure of merit of 17.4 fJ/conv step and Schreier FoM of 156.8 dB, respectively.

A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation

To design noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs) with high resolution and good power efficiency, two key bottlenecks need to be addressed. One is to realize a high-order loop filter with low circuit overhead, and the other is to mitigate the thermal noise. This article presents an NS-SAR ADC that synergistically addresses both challenges. To achieve high-order efficiency, it proposes an innovative error feedback-cascaded integrator feedforward (EF-CIFF) structure that realizes third-order noise shaping using only a single amplifier. It combines the merits of both structures, showing improved robustness, and is free of dc offset concern. On reducing the kT/C noise, this work features a sampling kT/C noise cancellation (SNC) technique that reuses the native hardware of the EF-CIFF structure. An open-loop self-quenching floating-inverter dynamic amplifier (FIDA) is used to support all amplification with low noise and power. Prototyped in 65-nm CMOS, this work achieves 84.8-dB signal-to-noise-distortion ratio (SNDR) with 625-kHz bandwidth (BW) (OSR = 8) and 119 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> , leading to 182-dB Schreier Figure of Merit (FoM). It uses only 0.8-pF input capacitance, which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times $ </tex-math></inline-formula> smaller than prior NS-SAR ADCs with similar oversampling ratio (OSR) and SNDR.

A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration

A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration

A 348-μW 68.8-dB SNDR 20-MS/s Pipelined SAR ADC With a Closed-Loop Two-Stage Dynamic Amplifier

This letter presents a two-stage dynamic amplifier that achieves the high dc gain and PVT robustness of the residue amplifier in a pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The proposed dynamic amplifier operates in a closed-loop configuration and does not require further calibration. The pipelined SAR ADC occupies 0.065 mm2 in a 65-nm CMOS process. It achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 68.8 dB at a sampling rate of 20 MS/s and draws 348 $\mu \text{W}$ from a 1.2-V supply. This corresponds to a Schreier FoM of 173.4 dB and a Walden FoM of 7.7 fJ/conv.-step. Furthermore, it maintains SNDRs over various sampling rates from 1 to 20 MS/s and its power consumption is scaled linearly.

A 74-dB Dynamic-Range 625-kHz Bandwidth Second-Order Noise-Shaping SAR ADC Utilizing a Temperature-Compensated Dynamic Amplifier and a Digital Mismatch Calibration

This paper presents the design of a 2nd-order Noise-Shaping (NS) Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) employing a cascade of temperature-compensated dynamic amplifier and a ring amplifier in the feedback path to realize a low-power/low-noise loop filter that is robust to temperature variation. A new mismatch calibration technique optimized for a noise-shaping SAR ADC is also presented to overcome the challenge of finding correct digital bit weights for NS SAR ADCs. Fabricated in 65 nm Complementary Metal-Oxide-Semiconductor (CMOS) process, the prototype ADC demonstrates a peak Signal-to-Noise-and-Distortion Ratio (SNDR) of 71.35 dB and a dynamic range of 74 dB with a signal bandwidth of 625 kHz. Over 80-degree of the temperature range, the ADC exhibits only 2 dB drop in SNDR thanks to the temperature-compensated dynamic amplifier. With a total power consumption of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$130~\mu \text{W}$ </tex-math></inline-formula> , the ADC achieves Walden Figure-of-Merit (FoM) of FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text {W}}= 34.4$ </tex-math></inline-formula> fJ and Schreier FoM of FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text {S,DR}}=171$ </tex-math></inline-formula> dB, respectively.

Static and dynamic bridge amplifier calibration according to ISO 4965-2

Dynamic measurements to correctly adjust the magnitude in fatigue testing require a dynamic calibration of force transducers and conditioning electronics if the dynamic loads are to be measured correctly. International standard ISO 4965 describes a calibration method for these components. At PTB, such a calibration of bridge amplifiers has now been performed for the first time. The calibration includes tests with static and dynamic signals. The reference for the calibration is the dynamic bridge standard of PTB. It is particularly suitable for this application as it can generate static and dynamic signals, and thus all investigations can be performed with one reference and in a reasonably short time. The signal creation and the data analysis were carried out using the open source program GNU Octave. For the data analysis, a semi-automatic procedure was developed to simplify the process. Calibrations of two digital bridge amplifiers were carried out.

An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS

An 8-bit 1-GS/s asynchronous loop-unrolled (LU) successive approximation register (SAR)-Flash hybrid analog-to-digital converter (ADC) with complementary dynamic amplifiers (CDAs) is presented. The proposed ADC is a combination of an asynchronous LU-SAR ADC and a reference-embedding 8 × interpolating flash (I-Flash) ADC to enhance the conversion speed. Operating the CDAs in a dual-edge manner makes it possible to achieve an 8-bit resolution with only four CDAs and one capacitive digital-to-analog converter (C-DAC), which improves the power and area efficiency as well as the input bandwidth. A prototype ADC implemented in a 28-nm CMOS process occupies a 0.002 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset calibration is 0.59 and 0.82 LSB, respectively. With a 0.499-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) are 45.5 and 59.4 dB, respectively. The measured effective resolution bandwidth (ERBW) is above 3 GHz. The power consumption at 1-GS/s conversion is 2.55 mW with a supply voltage of 1.1 V, leading to a figure of merit (FoM) of 16.6 fJ/conversion-step.

A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC

This article presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipeline analog-to-digital converter (ADC) incorporating various techniques to improve its bandwidth (BW), energy efficiency, and robustness. A multiple-input dynamic amplifier is used for both residue amplification and error feedback (EF) summation, thus realizing a 1st-order NS with low power consumption. An additional residue feed-forward (FF) path is introduced in the 2nd-stage SAR ADC to compensate for the noise transfer function (NTF) deterioration caused by the gain mismatch in the multiple-input pairs of the dynamic amplifier. The partial-interleaving 1st stage breaks the speed bottleneck of the conventional three-phase timing arrangement, which significantly enhances the overall ADC's speed and sampling performance. Besides, a coarse SAR ADC is introduced to further speed up the conversion with low power, while simultaneously enabling the enclosure of the data-weighted-averaging (DWA) on the DAC without a speed penalty. Finally, a low-cost inter-stage offset calibration is proposed that aligns the offset voltages among stages in the background without requiring an extra phase. Fabricated in the 28-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 75.2 dB over 40-MHz BW with only 7.5 over-sampling rate (OSR). Under a 1-V supply voltage, the ADC consumes 2.56 mW and exhibits a Scherier figure-of-merit (FoM) of 177.1 dB.

A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS

This paper presents a single-coarse dual-fine architecture that improves energy-efficiency of pipelined-SAR analog-to-digital converters (ADCs). A coarse and fast sub-ADC is used to quantize the most significant bits (MSBs), which are encoded with a proposed residue transformation method to control the residue generation of the first stages in two fine channels. The residue voltages generate on the capacitive digital-to-analog converters (C-DACs) of split fine channels directly without successive approximation processes. Therefore, the conversion rate is increased and the power is reduced. A shuffle mechanism is introduced into split-ADC based digital background calibration to avoid the divergence of the conventional algorithm in the proposed architecture. A high-energy-efficiency dynamic amplifier is also introduced as the residue amplifier. A 14-bit 60-MS/s ADC is prototyped in a 28-nm CMOS process. The digital calibration engine operates under 0.9-V supply, other parts of the ADC core operate under 1.05-V supply. The ADC core consumes 4.26 mW. Measurement results show that the calibration improved the signal-to-noise and distortion ratio (SNDR) and spur-free dynamic range (SFDR) dramatically, the calibrated ADC achieves SNDR and SFDR of 66.9 dB and of 91.0 dB respectively, translating to a Schreier FoM of 165.4 dB and a Walden FoM of 39.3 fJ/conversion-step.

A 10-kS/s 625-Hz-Bandwidth 65-dB SNDR Second-Order Noise-Shaping SAR ADC for Biomedical Sensor Applications

This paper introduces a low-power noise-shaping SAR ADC which is suitable for biomedical sensor applications. In this ADC, a low power consumption and area-efficient integrator is proposed, which is comprised of several switches, replica capacitors and a dynamic amplifier (DA). With a mode control logic circuit, the comparator in the ADC is reused as an amplifier for three times (three amplification phases) in a single conversion period to save area and power consumption. With the introduction of the first amplification phase, the additional capacitance can be greatly reduced without increasing overall kT/C noise. The second and third amplification phases decouple NTF zeros from the attenuation factor, allowing further area reduction. The comparator in amplification mode is designed more robust than prior arts. Fabricated in 0.18μm CMOS process, the prototype ADC has a 7-bit DAC and occupies a core area of 0.12mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Operating at 10kS/s, it consumes 90nW from a 1-V supply. At an OSR of 8, the SAR ADC achieves 65dB SNDR resulting in a FoMs of 163.5dB, and a FoMw of 50fJ/conv.-step.

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed closed-loop dynamic amplifier combines the merits of closed-loop architecture and dynamic operation, realizing robustness, high accuracy, and high energy-efficiency simultaneously. It is embedded in the loop filter of an NS SAR design, enabling the first fully dynamic NS-SAR ADC that realizes sharp noise transfer function (NTF) while not requiring any gain calibration. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 83.8 dB over a bandwidth of 625 kHz while consuming only $107~\mu \text{W}$ . It results in an SNDR-based Schreier figure-of-merit (FoM) of 181.5 dB.

A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier

This paper presents a process, voltage, and temperature (PVT)-insensitive dynamic amplifier (DA) with gain enhancement for a pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The gain shift due to temperature and process variation is attenuated through the counteraction of input transconductance and delay-based integration time. Furthermore, based on charge conservation, a gain-folding technique is proposed to improve the gain limit of conventional DA, tripling the gain amplitude. The proposed DA is incorporated in a design of a 12-bit 100 MS/s SAR ADC. In 65 nm CMOS process, at 100 MS/s, the prototype ADC achieves an SNDR (signal-to-noise plus distortion ratio) of 65.7 dB and a Walden FoM of 12.06 fJ/conversion-step for a near-Nyquist input. The power dissipation is less than 1.9 mW. No more than 1.65 dB SNDR variations are obtained for supply voltage varying from 1.15 to 1.25 V and temperature varying from −20 °C to 125 °C with various process corners, respectively.

A 65nm 0.6–1.2V Low-Dropout Regulator Using Voltage-Difference-to-Time Converter With Direct Output Feedback

This brief proposes a fully integrated output capacitor-less low-dropout regulator (LDO) using a voltage difference to time converter (VDTC). Proposed dynamic amplifier based VDTC allows low voltage operation and significantly reduces the quiescent current. The linear characteristics of VDTC result in output ripple-less operation and good regulation performance. Using direct output feedback through a small coupling capacitor, the gate voltage of the power transistor is instantly compensated to mitigate fluctuation of the output voltage when a sharp load transient occurs. Fabricated in 65 nm LP CMOS, the proposed LDO demonstrates a wide operation range with an input voltage range of 0.6-1.2 V and a load current of over 30 mA across all voltages without an output capacitor. With reduced output impedance due to direct output feedback, the measured undershoot is 158 mV, which is recovered in 9.6 μs, when the load current changes by 28 mA in 1 ns. The peak current efficiency is more than 99.99% and the figure of merit (FOM) is 0.202 fs. The active area of the control block is 0.002 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier

This article reports a high-linearity dynamic amplifier with a gain control technique for pipelined analog-to-digital converters (ADCs). The wide input range and dynamic operation of the amplifier allow the ADC energy-efficient pipeline process. The voltage gain is controlled in the analog domain with digital gain correction codes, enabling simple compensation for process, voltage, and temperature variations. The proposed switching technique for the amplifier also defines a stable common-mode output without any dedicated hardware. An 11-bit 100-MS/s fully dynamic pipelined ADC using the open-loop dynamic amplifier is implemented without gain-linearity calibration. An ADC prototype is fabricated in a 28-nm CMOS process with an active area of 0.05 mm2, and the performances are measured at sampling rates in the range of 10–100 MHz. This ADC achieves a signal-to-noise and distortion ratio of 62 dB and a spurious-free dynamic range of 77 dB while consuming 1.33 mW of power at 100 MS/s. A Walden figure of merit of 10.8–13.1 fJ/conversion-step is achieved.