A 10-kS/s 625-Hz-Bandwidth 65-dB SNDR Second-Order Noise-Shaping SAR ADC for Biomedical Sensor Applications

Abstract

This paper introduces a low-power noise-shaping SAR ADC which is suitable for biomedical sensor applications. In this ADC, a low power consumption and area-efficient integrator is proposed, which is comprised of several switches, replica capacitors and a dynamic amplifier (DA). With a mode control logic circuit, the comparator in the ADC is reused as an amplifier for three times (three amplification phases) in a single conversion period to save area and power consumption. With the introduction of the first amplification phase, the additional capacitance can be greatly reduced without increasing overall kT/C noise. The second and third amplification phases decouple NTF zeros from the attenuation factor, allowing further area reduction. The comparator in amplification mode is designed more robust than prior arts. Fabricated in 0.18μm CMOS process, the prototype ADC has a 7-bit DAC and occupies a core area of 0.12mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Operating at 10kS/s, it consumes 90nW from a 1-V supply. At an OSR of 8, the SAR ADC achieves 65dB SNDR resulting in a FoMs of 163.5dB, and a FoMw of 50fJ/conv.-step.