Dual Stress Liner Research Articles

Numerical Study on SEU Performance of Strain Engineered 6T-SRAM Cells

In this work, the impact of shallow trench isolation (STI) and dual stress liner (DSL) -induced stresses on soft error performance of 30-nm gate length Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET)-based 6T-SRAM cells is studied using process and device simulations. Under nine different stress combinations, i.e., nine different SRAMs, our simulation results show that the stresses introduced from STI and DSL enhance the soft error performance of the cells significantly.

Strain Modification of PECVD Nitride By Plasma Immersion Ion Implantation Processes

Strain engineering was introduced in the microelectronics industry almost two decades ago to improve the carrier mobility due to the modification of the band structures in the Metal Oxide Field Effect Transistor (MOSFET) channel [1, 2]. One method to induce local strain in the transistor channel consists in using Contact Etch Stop Layer (CESL) as stress liner. In order to improve both n-MOS and p-MOS performance, the use of a dual stressed liner (DSL) integration is a solution that combines tensile and compressive films on the same wafer [3]. However, the poor mechanical stability of the compressive PECVD nitride layer when exposed to a high thermal budget, combined with the increased integration complexity, limits the interest of the DSL approach. An alternative solution to tackle these limitations consists in locally transforming the tensile CESL nitride into compressive by Plasma Immersion Ion Implantation (PIII).For this study, PIII processes were performed on 300mm silicon bare wafers capped with a 35nm tensile PECVD nitride. Various species (Hydrogen (H), Helium (He) and Nitrogen (N)) implanted at various acceleration voltages (increasing from 1 to 6 in arbitrary units) and doses (A<B<C) were studied using a Pulsion® tool manufactured by IBS. After these processes, the samples were characterized by various techniques such as ellipsometry, bow measurement, Scanning Electron Microscopy observations, Secondary Ion Mass Spectrometry or FTIR analysis.The stress of the various nitride layers was determined by the Stoney formula, using the curvature measurements and the layer thickness determined by ellipsometry, assuming the shift of the bow results only from the change in nitride stress. Results show that, for all the species studied, the PIII process provides the capability to change the nitride stress from initially tensile to neutral or even compressive when increasing the dose and the acceleration voltage (Fig.1). The largest stress modifications were achieved with nitrogen and hydrogen. For the latter however, the blistering of the nitride layer is observed for the highest doses due to an excessive hydrogen concentration, which is prohibitive for further process integration. By using helium PIII process, the stress change is less for identical process parameters (Fig.1), leading to a neutrally stressed nitride layer. Increasing the helium dose to modify the nitride stress further leads to a consumption of the layer, which limits the use of helium only to the reversal of the mechanical stress.To verify that the stress change will remain during the subsequent process steps, curvature measurements were performed after a consequent thermal budget, equivalent to PMD deposition, applied after the PIII processes. The results show no significant change of the stress level.We demonstrated the capability of PIII processes to turn a tensile CESL nitride layer into a compressive one in a reasonable processing time thanks to the high beam current achievable with PIII process, without any consumption of the layer and without the need of a post implantation thermal treatment. Complementary analysis are on-going to fully characterize the impact of each species on the CESL physicochemical properties and thereby understand its stress evolution. Thanks to these encouraging results, the most promising conditions of all the species mentioned above will be experimented on electrical structures to quantify the related static performance gain.This project (OCEAN12) has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 783127. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and France, Germany, Austria, Portugal, Greece, Spain, Poland.[1] S. Ito, et al, “Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”, 2000 IEDM Tech. Dig., p. 247[2] T.K. Kang, IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 6, JUNE 2012.[3] H. S. Yang, “Dual Stress Liner for High Performance sub-45nm Gate Length SO1 CMOS Manufacturing”, IEDM 2004 Figure 1

Performance enhancement of c-CESL-strained 95-nm-gate NMOSFET using trench-based structure

A stress modulation technology using a trench-based structure for strained NMOSFET is reported in this paper. With this technology, NMOSFET can be improved by a compressive contact etch stop layer (CESL), whereas the traditional CESL-strained NMOSFET requires a tensile one. To confirm this idea, a 95-nm-gate device with a −2.5 GPa strained CESL is simulated to investigate the effects of the trench-based structure on channel stress. It is demonstrated that the average longitudinal channel stress is transformed from −333 into 256 MPa, which leads to a significant improvement of the device's I–V performance. For strained CMOS, this approach provides a potential alternative besides dual stress liner technology.

Integration Issue of Tensile SiN Liner for Dual Stress Liner(DSL) in Gate-Last High-k/Metal Gate(HKMG) Process Flow

In this paper, a process challenge of integrating Dual Stress Liner (DSL) (1)-(2) into gate-last High-k/Metal Gate (HKMG) flow is explained and a solution is presented. DSL is an effective method to enhance carriers’ mobility for short channel devices. But when it is applied to gate-last HKMG flow, the dummy gate oxide removal step (wet etch by DHF solution) would result in significant etch of tensile SiN liner. Because tensile SiN liner is formed on gate spacers and is exposed after Poly-Open-Polish (POP) CMP, recesses at the sides of the gate stacks would be formed during dummy gate oxide etch. In order to solve this problem, tensile SiN liner is treated in N2 plasma to reduce it’s etch rate in DHF solution. As a result, no recess appears at the side of gate stacks in our devices during the dummy gate oxide removal step.

Dry Etching Solutions to Contact Hole Profile Optimization for Advanced Logic Technologies

As CMOS technology has been continuously scaling down and the dual-stress liner scheme is introduced for simultaneous stress enhancement of both n-MOS and p-MOS, contact etch has started to act as a critical role for the robust performance of integrated circuit. In this work, we investigated the impact of dry etching process on contact hole profile. Results demonstrate the overall contact hole profile can be rigorously controlled if the radio frequency (rf) powers and etching chemistries in inter layer dielectric (ILD) etch step are well balanced. Free local pull-back at contact hole sidewall has to leverage the optimization of etch selectivity of silicon nitride over silicon oxide in liner removal step. Besides, the post etch treatment (PET) is also proven to be imperative for the process window enhancement for such pull-back reduction.

Self-Annealing Effect of Tensile Liner on Thick-Tinv PMOS

Various techniques have been applied in modern CMOS technology to passivate interface traps, thus improving digital performance and reliability. Although these methods are effective, they all clearly add process complexity and cost. In this paper, a novel method, without adding a single extra step, is introduced to reduce thick-Tinv PMOS interface trap density. Experimental results confirm that depositing a tensile liner film first in the dual stress liner process can reduce the interface trap density of thick-Tinv PMOS effectively. The passivation, which is verified by charge pumping results, is believed to be due to the annealing effect of the hydrogen in the tensile liner driven by the UV anneal step used in stress transfer.

Extension of Moore's Law via Strained Technologies- The Strategies and Challenges

In this paper, we will first give an overview on the strain-silicon technology, such as eSiGe, eSi:C, stress memorization technique (SMT), dual stress liners (DSL), and high-k/metal gate replacement gate (RMG) process, after the 90nm generation. Then, the reliability and the design guideline for a trade-off between performance and reliability will be addressed. A technology roadmap in terms of the ballistic transport theory will be outlined. Then, the variability of the strained CMOS devices with focus on the discrete dopant profiling will be demonstrated. Finally, the strategies of strained-silicon device on advanced 3D device structure and IC will be introduced.

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies.

Layout Variation Effects in Advanced MOSFETs: STI-Induced Embedded SiGe Strain Relaxation and Dual-Stress-Liner Boundary Proximity Effect

This paper reports two areas of focus for layout variation effects in advanced strained-Si technology: 1) shallow-trench isolation (STI)-induced embedded SiGe (eSiGe) strain relaxation and 2) impact of dual-stress-liner (DSL) boundary on channel mobility. A complete data analysis, including two different strain measurement techniques of nanobeam diffraction and geometric phase analysis, is presented, along with a quantitative understanding for each effect. It is reported that the eSiGe profile can have a significant impact on the STI proximity effect for p-MOSFETs and that DSL boundary proximity can cause significant channel mobility degradation for both n- and p-MOSFETs. Both effects result in the reduction in channel strain along the [110] direction.

High-Performance Metal/High-$k$ n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

Newly proposed mobility-booster technologies are demonstrated for metal/high-k gate-stack n- and pMOSFETs. The process combination of top-cut SiN dual stress liners and damascene gates remarkably enhances local channel stress particularly for shorter gate lengths in comparison with a conventional gate-first process. Dummy gate removal in the damascene gate process induces high channel stress, because of the elimination of reaction force from the dummy gate. PFETs with top-cut compressive stress liners and embedded SiGe source/drains are performed by using atomic layer deposition TiN/HfO2 gate stacks with Tinv=1.4 nm on (100) substrates. On the other hand, nFETs with top-cut tensile stress liners are obtained by using HfSix/HfO2 gate stacks with Tinv=1.4 nm. High-performance n- and pFETs are achieved with Ion=1300 and 1000 muA/mum at Ioff =100 nA/mum, Vdd=1.0 V, and a gate length of 40 nm, respectively.

A Study of Stress Technology for 65nm Generic CMOS Technology

For deep sub-100nm CMOS technology, the stress level impacts transistor performance significantly. In this paper, we present the investigation results of stress technology in a 65 nm generic process. We studied some mobility enhancing technologies such as Stress-Memorization Technology (SMT) and Dual Stress Liner (DSL) process in a conventional 65 nm Generic CMOS process. The transistor performance with different stress layers and stress levels are reported. The experimental results show that SMT and higher stress level tensile ESL (Etch-Stop Layer) improve NMOS performance while compressive ESL improve PMOS significantly. For the required-device performance, the stress layer and stress architecture should be carefully optimized. The stress technology reported in this paper has been successfully implemented in the production of 65 nm generic process.

Stress Liner Proximity Technique to Enhance Carrier Mobility in High-κ Metal Gate MOSFETs

AbstractFor the first time, we discuss the compatibility of stress proximity technique (SPT) with dual stress liner (DSL) in high-κ/metal gate (HK/MG) technology. The short-channel mobility enhancement and the drive current improvement brought by SPT have been demonstrated at 32nm technology node. With maintained short channel control and threshold voltage roll-off characteristics, SPT has achieved 7% drive current improvement for both nFET and pFET from the optimization of SPT with DSL.

Effect of STI, DSL and SMT on f T and noise-figure in 30 nm gate length NMOSFET

The effect of stress, in particular, shallow trench isolation, dual stress liner (DSL) and stress memorisation technique (SMT) on unity gain cut-off frequency (f T) and noise-figure (NF) of 30 nm gate length nMetal-oxide-semiconductor field-effect transistors (nMOSFET) has been studied, using extensive process and device simulations. The simulations include many of the latest process steps, like high-K dielectric, metal gate, laser annealing and stress engineering aspects. The results have been compared with the hypothetical MOSFET where the device is set to be stress-free. Simulation results show that DSL improves both f T and NF whereas SMT technique improves f T and degrades the noise performance.