Abstract
In this paper, a process challenge of integrating Dual Stress Liner (DSL) (1)-(2) into gate-last High-k/Metal Gate (HKMG) flow is explained and a solution is presented. DSL is an effective method to enhance carriers’ mobility for short channel devices. But when it is applied to gate-last HKMG flow, the dummy gate oxide removal step (wet etch by DHF solution) would result in significant etch of tensile SiN liner. Because tensile SiN liner is formed on gate spacers and is exposed after Poly-Open-Polish (POP) CMP, recesses at the sides of the gate stacks would be formed during dummy gate oxide etch. In order to solve this problem, tensile SiN liner is treated in N2 plasma to reduce it’s etch rate in DHF solution. As a result, no recess appears at the side of gate stacks in our devices during the dummy gate oxide removal step.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
