Abstract
In this work, the impact of shallow trench isolation (STI) and dual stress liner (DSL) -induced stresses on soft error performance of 30-nm gate length Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET)-based 6T-SRAM cells is studied using process and device simulations. Under nine different stress combinations, i.e., nine different SRAMs, our simulation results show that the stresses introduced from STI and DSL enhance the soft error performance of the cells significantly.
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