Investigation of STI edge effect on programming disturb in localized charge trapping SONOS flash memory cells

Abstract

Abstracts The impact of shallow trench isolation (STI) on non-volatile memories has become much more serious for sub-90-nm CMOS technologies. This paper uses the localized charge trapping polysilicon-oxide-nitride-oxide-silicon (SONOS) flash memory cells to investigate STI edge effect on programming disturb when the channel hot electron injection programming method is applied. The different programming disturbs between the central cells far from STI and the edge cells close to STI are experimentally presented on the array level. At the programmed state, the edge cells suffer larger decrease of threshold voltage compared to the central cells under the same drain disturb. However, both edge and central cells at the erased state have not any significant variations of threshold voltage distribution under the same disturb conditions. In addition, both edge and central cells demonstrate almost the same behaviors under gate disturb. Two-dimension process simulation results show that the edge cells suffer a higher compressive stress caused from STI corner than the central cells. The higher compressive stress increases hole mobility, which is mainly responsible for the relatively serious drain disturb in the programmed edge cells.