Self-Annealing Effect of Tensile Liner on Thick-Tinv PMOS

Abstract

Various techniques have been applied in modern CMOS technology to passivate interface traps, thus improving digital performance and reliability. Although these methods are effective, they all clearly add process complexity and cost. In this paper, a novel method, without adding a single extra step, is introduced to reduce thick-Tinv PMOS interface trap density. Experimental results confirm that depositing a tensile liner film first in the dual stress liner process can reduce the interface trap density of thick-Tinv PMOS effectively. The passivation, which is verified by charge pumping results, is believed to be due to the annealing effect of the hydrogen in the tensile liner driven by the UV anneal step used in stress transfer.