Dual-gate Operation Research Articles

Dual-Gate Operation and Configurable Logic From Solution Pattern-Based Zinc Tin Oxide Thin-Film Transistors

Dual-Gate Operation and Configurable Logic From Solution Pattern-Based Zinc Tin Oxide Thin-Film Transistors

Impact of Dual-Gate Configuration on the Endurance of Ferroelectric Thin-Film Transistors With Nanosheet Polycrystalline-Silicon Channel Film

This work explores the characteristics of ferroelectric thin-film transistors (FeTFTs) utilizing an asymmetric dual-gate (DG) structure in both single-gate (SG) and DG operation modes. In the transfer characteristics, DG mode exhibits a memory window (MW) of 1.075 V, smaller than SG mode’s MW of 1.402 V, attributed to the back-gate bias effect causing a reduction in the device’s threshold voltage. However, DG mode demonstrates superior endurance characteristics with 106 cycles compared to SG mode’s 105 cycles. Additionally, the increase in erase pulse voltage (VERS) exacerbates the polycrystalline-silicon channel lattice damage of FeTFT, resulting in subthreshold swing (SS) degradation. Nevertheless, the extent of SS degradation from DG mode operation is significantly lower than that of SG mode, contributing to the superior endurance of DG mode. The elevation of program pulse voltage (VPRG) induces imprint and charge-trapping effects in the top-gate ferroelectric dielectric, leading to reduced endurance. Due to the use of SiO2 as the back-gate dielectric in FeTFT, DG mode exhibits lower impacts of charge-trapping effects from the top-gate ferroelectric dielectric layer, resulting in better endurance compared to SG mode. The asymmetric DG structure provides greater tolerance in the selection of VPRG and VERS.

Exploring Performance and Reliability Behavior of Nanosheet Channel Thin-Film Transistors under Independent Dual Gate Bias Operation

In this work, the polycrystalline-silicon (poly-Si) thin-film transistor with an independent dual-gate (IDG) structure and ultra-thin nanosheet channel (∼4 nm) is fabricated to investigate the impacts of different dual-gate operation modes on device performance and reliability. Compared to the single top-gate (TG) operation mode, the double-gate (DG) operation mode exhibits superior threshold voltage (VTH), subthreshold swing, and saturation current in the device. In addition, the DG operation mode also shows better reliability behavior of positive gate bias stress (PGS) due to the enhanced control capability of the gate voltage on the channel potential. Under the single TG operation mode, the independent back-gate voltage (VBG) can effectively modulate the device’s VTH to meet circuit design requirements. Using a fixed positive VBG can not only reduce the VTH of the device, but also decrease the damage caused by the PGS on the device due to the buried channel effect generated by the ultra-thin nanosheet channel, which increases the coupling capacitance thickness between the buried channel and the top-gate oxide layer. On the contrary, using a negative VBG will enhance the PGS degradation of TG. Consequently, the positive VBG is suggested to lower the VTH and improve the PGS of the device.

Pushing the Limits of Biosensing: Selective Calcium Ion Detection with High Sensitivity via High-k Gate Dielectric Engineered Si Nanowire Random Network Channel Dual-Gate Field-Effect Transistors.

Calcium ions (Ca2+) are abundantly present in the human body; they perform essential roles in various biological functions. In this study, we propose a highly sensitive and selective biosensor platform for Ca2+ detection, which comprises a dual-gate (DG) field-effect transistor (FET) with a high-k engineered gate dielectric, silicon nanowire (SiNW) random network channel, and Ca2+-selective extended gate. The SiNW channel device, which was fabricated via the template transfer method, exhibits superior Ca2+ sensing characteristics compared to conventional film channel devices. An exceptionally high Ca2+ sensitivity of 208.25 mV/dec was achieved through the self-amplification of capacitively coupled DG operation and an enhanced amplification ratio resulting from the high surface-to-volume ratio of the SiNW channel. The SiNW channel device demonstrated stable and reliable sensing characteristics, as evidenced by minimal hysteresis and drift effects, with the hysteresis voltage and drift rate measuring less than 6.53% of the Ca2+ sensitivity. Furthermore, the Ca2+-selective characteristics of the biosensor platform were elucidated through experiments with pH buffer, NaCl, and KCl solutions, wherein the sensitivities of the interfering ions were below 7.82% compared to the Ca2+ sensitivity. The proposed Ca2+-selective biosensor platform exhibits exceptional performance and holds great potential in various biosensing fields.

Enhanced channel modulation in Aluminum- and Hydrogen-Doped Zinc-Oxide-Based transistors by complementary Dual-Gate operation

This study elucidates the enhanced channel modulation by the dual-gate operation of the ultrathin ZnO-based field-effect transistors (FETs). Bottom-gate atomic-layer-deposited zinc oxide (ZnO) transistors exhibit typical n-type enhancement-mode transfer characteristics. However, when equipped with the top Al2O3 layer, the FETs exhibit conductive transfer characteristics. These electrical property changes are attributed to Al2O3-induced hydrogen and aluminum doping effects, which increase carrier concentration. Although Al2O3-induced doping increased field-effect mobility by a factor of 2, a high off current and degraded transconductance swing were observed in FETs. However, operation in dual-gate mode after the deposition of the top-gate electrode resolved these degradations and led to achieving high-performance ZnO FETs: the off current significantly decreased, and noteworthy, field-effect mobility increased by a factor of 5. Temperature-dependent charge transport analysis revealed that the complementary dual-gate operation efficiently filled the localized trap states in the ZnO films, resulting in band-like transport. Thus, it is deduced that the complementary dual-gate operation enhanced channel modulation in the Al2O3-induced hydrogen- and aluminum-doped ZnO channel, resulting in high-performance ZnO FETs.

Impacts of Independent Dual-Gate Operation on Reliability of Nanosheet Junctionless Thin-Film Transistor

In this work, impacts of the independent dual-gate (IDG) operation on performance and reliability of the polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) with a nanosheet channel (~4 nm) are investigated. Compared to the single-gate (SG) operation, the JL-TFT with tied dual gate (DG) operation times maximum transconductance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${G}_{m\_{}{\text {max}}}$ </tex-math></inline-formula> ) improvement and 3.3 times driving current enhancement. The tied DG operation also exhibits better gate bias stress immunity than the SG operation although the tied DG stress causes more serious damages to the JL-TFT than the SG stress. As for the independent back gate (BG) voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> ) operation mode, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> can provide a wide threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> ) tuning range ~2 V when the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> is modulated from 0 to −4 V. The negative <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> bias stress would induce electron injection from the BG, resulting in positive <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shift. Because the positive top gate voltage stress exhibits more serious electrical degradation than the negative <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> stress, using <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> to modulate the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> of the JL-TFT will cause a slightly more serious reliability issue. The results show the feasibility of using independent <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> to adjust the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> of the JL-TFTs to meet the multiple- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> requirement of advanced integrated circuits.

MoTe2 on ferroelectric single-crystal substrate in the dual-gate field-effect transistor operation

An exfoliated MoTe2 flake in contact with a ferroelectric single-crystal substrate was studied to examine its charge carrier modulation by neighboring ferroelectric polarization. A MoTe2 field-effect transistor was fabricated, having a hexagonal-BN (hBN) flake and a ferroelectric substrate employed as top and bottom gate dielectrics. In the dual-gate operation, the charge conduction exhibited an ambipolar behavior with large hysteresis during the gate voltage sweep. It mainly originates from the ferroelectric nature in combination with the charge trap phenomena at the interfaces. Interestingly, we found out that holes are more easily trapped than electrons, and charge carriers in MoTe2 are easily modulated through the top hBN gate when the electron conduction is predominantly set by the bottom ferroelectric field. However, the controllability becomes much weaker under opposing ferroelectric polarizations. This unbalanced controllability reveals the interfacial hole-trap effect resulting from ferroelectric polarization.

Toward ultraviolet solution processed ZrOx/IZO transistors with top-gate and dual-gate operation: Selection of solvents, precursors, stabilizers, and additive elements

Low-temperature processed oxide thin-film transistors (TFTs) have been developed by the process of solution-processed metal oxide films using deep ultraviolet (UV) irradiation, although they still suffer from relatively poor electrical performance and severe electrical and chemical instability. This UV coating solution essentially involves chemical damage from acidic or basic precursor ligands; therefore, the top-gate and dual-gate TFTs suffer structurally inherent chemical damage, which limits the freedom of process design. An engineering concept solution using the four functional components of solvent, precursor, stabilizer, and additive was suggested for UV solution coating of high-k zirconium oxide (ZrOx). Here the proposed solvent, stabilizer, precursor, and additive include polar-aprotic N,N-methylformamide, zirconium acetylacetonate, ethanolamine, and oleic acid for polar-aprotic solution, effective photolysis, complete precursor dissolution, and high densification, respectively. The ultrathin ZrOx (15 nm) revealed a low leakage current density of <10−11 mA/cm2 at 1 MV/cm, good breakdown voltage, and a constant capacitance of approximately 260 nF/cm2 at 1 MHz. Similar transfer characteristics of both the bottom and top gates, and a field-effect mobility of 24 cm2/V, without degradation of subthreshold swing and threshold voltage values in the dual-gate, were involved in the chemically durable process and the dense coating conditions of ZrOx, regardless of the IZO and ZrOx stacking sequence.

Ultralow Power Dual Gated Sub-Threshold Oxide Neuristors: An Enabler for Higher Order Neuronal Temporal Correlations

Inspired by neural computing, the pursuit of ultralow power neuromorphic architectures with highly distributed memory and parallel processing capability has recently gained more traction. However, emulation of biological signal processing via artificial neuromorphic architectures does not exploit the immense interplay between local activities and global neuromodulations observed in biological neural networks, and hence are unable to mimic complex biologically plausible adaptive functions like heterosynaptic plasticity and homeostasis. Here, we demonstrate emulation of complex neuronal behaviours like heterosynaptic plasticity, homeostasis, association, correlation and coincidence in a single neuristor via a novel dual-gated architecture. This multiple gating approach allows one gate to capture the effect of local activity correlations and the second gate to represent global neuromodulations, allowing additional modulations which augment their plasticity and enabling higher order temporal correlations at a unitary level. Moreover, the dual-gate operation extends the available dynamic range of synaptic conductance while maintaining symmetry in the weight-update operation, expanding the number of accessible memory states. Finally, operating neuristors in the sub-threshold regime enables synaptic weight changes with high gain, while maintaining ultralow power consumption of the order of femto-Joules.

A Novel Blood-Based Colorectal Cancer Diagnostic Technology Using Electrical Detection of Colon Cancer Secreted Protein-2.

Colorectal cancer (CRC) is the second‐leading cause of cancer‐related mortality worldwide, which may be effectively reduced by early screening. Colon cancer secreted protein‐2 (CCSP‐2) is a promising blood marker for CRC. An electric‐field effect colorectal sensor (E‐FECS), an ion‐sensitive field‐effect transistor under dual gate operation with nanostructure is developed, to quantify CCSP‐2 directly from patient blood samples. The sensing performance of the E‐FECS is verified in 7 controls and 7 CRC samples, and it is clinically validated on 30 controls, 30 advanced adenomas, and 81 CRC cases. The concentration of CCSP‐2 is significantly higher in plasma samples from CRC and advanced adenoma compared with controls (both P < 0.001). Sensitivity and specificity for CRC versus controls are 44.4% and 86.7%, respectively (AUC of 0.67), and 43.3% and 86.7%, respectively, for advanced adenomas (AUC of 0.67). CCSP‐2 detects a greater number of CRC cases than carcinoembryonic antigen does (45.6% vs 24.1%), and the combination of the two markers detects an even greater number of cases (53.2%). The E‐FECS system successfully detects CCSP‐2 in a wide range of samples including early stage cancers and advanced adenoma. CCSP‐2 has potential for use as a blood‐based biomarker for CRC.

Ultralow Power Dual-Gated Subthreshold Oxide Neuristors: An Enabler for Higher Order Neuronal Temporal Correlations.

Inspired by neural computing, the pursuit of ultralow power neuromorphic architectures with highly distributed memory and parallel processing capability has recently gained more traction. However, emulation of biological signal processing via artificial neuromorphic architectures does not exploit the immense interplay between local activities and global neuromodulations observed in biological neural networks and hence are unable to mimic complex biologically plausible adaptive functions like heterosynaptic plasticity and homeostasis. Here, we demonstrate emulation of complex neuronal behaviors like heterosynaptic plasticity, homeostasis, association, correlation, and coincidence in a single neuristor via a dual-gated architecture. This multiple gating approach allows one gate to capture the effect of local activity correlations and the second gate to represent global neuromodulations, allowing additional modulations which augment their plasticity, enabling higher order temporal correlations at a unitary level. Moreover, the dual-gate operation extends the available dynamic range of synaptic conductance while maintaining symmetry in the weight-update operation, expanding the number of accessible memory states. Finally, operating neuristors in the subthreshold regime enable synaptic weight changes with high gain while maintaining ultralow power consumption of the order of femto-Joules.

Dual-gate operation and carrier transport in SiGe p–n junction nanowires

We investigate carrier transport in silicon–germanium nanowires with an axial p–n junction doping profile by fabricating these wires into transistors that feature separate top gates over each doping segment. By independently biasing each gate, carrier concentrations in the n- and p-side of the wire can be modulated. For these devices, which were fabricated with nickel source–drain electrical contacts, holes are the dominant charge carrier, with more favorable hole injection occurring on the p-side contact. Channel current exhibits greater sensitivity to the n-side gate, and in the reverse biased source–drain configuration, current is limited by the nickel/n-side Schottky contact.

Characterization of a 1024 × 1024 DG-BioFET platform

The use of biological field effect transistors (BioFETs) for the detection of biochemical events will yield new sensing systems that are smaller, less expensive, faster, and capable of multiplexing. Here, we present a novel massively parallel dual-gated BioFET (DG-BioFET) platform with over a million transistors in a 7×7mm2 array that has all these benefits. Utilizing on-chip integrated circuits for row and column addressing and a PXI IC tester to measure signals, the drain current of each sensor in the 1024×1024 array is serially acquired in just 90s. In this paper, we demonstrate that sensors in our massively parallel platform have standard transfer characteristics, high pH-sensitivity, and robust performance. In addition, we use the dual-gate operation and fast acquisition, unique in our platform, to improve the sensing performance of the system. We show that tailored biasing of the two DG-BioFET gates results in signal amplification above the Nernst limit (to 84mV/pH) and redundancy techniques facilitate differential referencing, improving the resulting signal-to-noise ratio. Our platform encompasses the advantages of semiconductor-based biosensors, and demonstrates the benefits of high parallelism and FET dual-gate amplification for electrical and miniaturized biological sensing.

Back-Channel Electrolyte-Gated a-IGZO Dual-Gate Thin-Film Transistor for Enhancement of pH Sensitivity Over Nernst Limit

A dual-gate amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) was studied to obtain a pH sensitivity of $\sim 160$ mV/pH, which is above Nernst limit (59 mV/pH) with a low value of operating voltage (−5 to 5 V). The utilization of the active layer itself as the sensitive surface constitutes the dual-gate TFT structure with the back-channel gated with the electrolyte. The TFT characteristics were optimized by annealing the IGZO film in varying temperatures in oxygen ambience. A double-layered a-IGZO was used to sandwich the source/drain electrodes to eliminate the issues related with the high contact resistance and critical passivation of source/drain electrodes to protect from the exposure of the electrolyte. The single-gate electrolyte-gated thin film transistor showed the pH sensitivity of 24 mV/pH, which was enhanced by 6.7-fold by its dual-gate operation. The operation of dual-gate TFT ion-sensitive field-effect transistors (ISFETs) with varying only bottom gate voltage eliminates the requirement of a reference electrode necessary in single-gate ISFETs. Such dual-gate ISFETs obviate the need of an additional high- $K$ dielectric needed for the dual-gate TFT ISFETs and could also be fabricated on flexible substrates. These structures with the high sensitivity of $\sim 160$ mV/pH and requiring low ( $\sim 2~\mu \text{L}$ ) analyte solution could be the potential candidates for utilization as chemical and bio-sensors.

Dual-Gate MoS2FET With a Coplanar-Gate Engineering

A dual-gate multilayer MoS2 FET with a standard backside gate and a nonstandard coplanar top gate is demonstrated and analyzed. The special feature of this device is that the gate and MoS2 channel can be directly coupled on the same plane through the bottom-conducting Si substrate. The coplanar-gate MoS2 FET shows a good performance with a large ON–OFF ratio ( $I_{\mathrm{\scriptscriptstyle {ON/OFF}}}$ ) of $1.5\times 10^{4}$ , a small subthreshold swing ( $S$ ) of 0.13 V/decade, and a field-effect mobility ( $\mu $ ) of 0.69 cm2/Vs, respectively. Furthermore, a large $V_{\mathrm {{th}}}$ modulation ( $- 0.55\sim 6.4$ V) can be obtained in a dual-gate MoS2 FET by changing the coplanar-gate bias, which makes the device switch from depletion-mode to enhancement-mode operation, without affecting $\mu $ and $S$ , regardless of the coplanar-gate bias. In such a dual-gate MoS2 FET, both top and bottom gates can share the same SiO2 dielectric, and the deposition of source/drain/gate contact can be combined to a single step. A band diagram with the body effect theory is proposed to explain the device operation mechanism. The coplanar-gate MoS2 FET with its dual-gate operation and simple fabrication process can provide a good candidate for low-cost 2-D planar nanoelectronics and sensor applications.

Dual Gate Charge Trap Flash Memory for Highly Reliable Triple Level Cell using Capacitive Coupling Effects

In this letter, the triple level cell (TLC) NAND flash memory with excellent properties was implemented by a thin film charge trap flash memory with a dual-gate structure by using the capacitive coupling effect between the front gate and back gate. As compared with the single-gate (SG) mode operation, a large memory window at low program and erase (P/E) voltages was obtained from the dual-gate (DG) mode operation owing to the capacitive coupled self-amplifying effect. The TLC was implemented by using the DG-mode operation with highly stable eight levels: a large threshold voltage difference >9 V per level was obtained under low operating voltages at $100~\mu \text{s}$ . In contrast, the conventional SG mode was unfavorable to TLC. Furthermore, the DG mode showed a much smaller charge loss than the SG mode, resulting in stable retention and endurance characteristics at room temperature and high temperature.

Enhancing the pH sensitivity by laterally synergic modulation in dual-gate electric-double-layer transistors

The sensitivity of a standard ion-sensitive field-effect transistor is limited to be 59.2 mV/pH (Nernst limit) at room temperature. Here, a concept based on laterally synergic electric-double-layer (EDL) modulation is proposed in order to overcome the Nernst limit. Indium-zinc-oxide EDL transistors with two laterally coupled gates are fabricated, and the synergic modulation behaviors of the two asymmetric gates are investigated. A high sensitivity of ∼168 mV/pH is realized in the dual-gate operation mode. Laterally synergic modulation in oxide-based EDL transistors is interesting for high-performance bio-chemical sensors.

A self-amplified transistor immunosensor under dual gate operation: highly sensitive detection of hepatitis B surface antigen.

Ion-sensitive field-effect transistors (ISFETs), although they have attracted considerable attention as effective immunosensors, have still not been adopted for practical applications owing to several problems: (1) the poor sensitivity caused by the short Debye screening length in media with high ion concentration, (2) time-consuming preconditioning processes for achieving the highly-diluted media, and (3) the low durability caused by undesirable ions such as sodium chloride in the media. Here, we propose a highly sensitive immunosensor based on a self-amplified transistor under dual gate operation (immuno-DG ISFET) for the detection of hepatitis B surface antigen. To address the challenges in current ISFET-based immunosensors, we have enhanced the sensitivity of an immunosensor by precisely tailoring the nanostructure of the transistor. In the pH sensing test, the immuno-DG ISFET showed superior sensitivity (2085.53 mV per pH) to both standard ISFET under single gate operation (58.88 mV per pH) and DG ISFET with a non-tailored transistor (381.14 mV per pH). Moreover, concerning the detection of hepatitis B surface antigens (HBsAg) using the immuno-DG ISFET, we have successfully detected trace amounts of HBsAg (22.5 fg mL(-1)) in a non-diluted 1× PBS medium with a high sensitivity of 690 mV. Our results demonstrate that the proposed immuno-DG ISFET can be a biosensor platform for practical use in the diagnosis of various diseases.

SOI dual-gate ISFET with variable oxide capacitance and channel thickness

A dual-gate (DG) ion sensitive field effect transistor (ISFET) using capacitance coupling effect has recently been proposed to overcome the Nernst limitation as 59mV/pH. In this study, we focus on the analysis of sensing characteristics by various oxide capacitances and channel thickness using intensive measurement on conventional fully depleted (FD) silicon-on-insulator (SOI) based DG ISFET. The enlarged oxide capacitance and reductive channel thickness enhance the capacitive coupling effect and increase sensitivity of DG ISFET. And also, the thin channel thickness reduced the leakage current in the DG operation. These will be very promising techniques for high performance biosensor application.

High-Current-Drive Dual-Gate a-IGZO TFT With Nanometer Dotlike Doping

In this letter, we use a dual-gate (DG) structure together with nanometer dotlike doping (NDD) in active channel to produce a-IGZO thin-film transistors with very high current drive. With DG operation, the output current increases from 0.14 mA of the conventional device to 0.76 mA of the NDD device. The enhanced lateral field and improved carrier accumulation in DG operation may explain the significantly enlarged drive current. Particularly, simulated electron distribution reveals that high carrier concentration is induced under NDD regions in DG operation. The device without NDD, however, does not exhibit improved drive current in DG operation.