Dual-gate Operation Research Articles

Programmable ion-sensitive transistor interfaces. I. Electrochemical gating

Electrochemical gating is the process by which an electric field normal to the insulator electrolyte interface shifts the surface chemical equilibrium and further affects the charge in solution [Jiang and Stein, Langmuir 26, 8161 (2010)]. The surface chemical reactivity and double-layer charging at the interface of electrolyte-oxide-semiconductor (EOS) capacitors is investigated. We find a strong pH-dependent hysteresis upon dc potential cycling. Varying salinity at a constant pH does not change the hysteretic window, implying that field-induced surface pH regulation is the dominant cause of hysteresis. We propose and investigate this mechanism in foundry-made floating-gate ion-sensitive field-effect transistors, which can serve as both an ionic sensor and an actuator. Termed the chemoreceptive neuron metal-oxide-semiconductor (CνMOS) transistor, it features independently driven control gates (CGs) and sensing gates (SGs) that are capacitively coupled to an extended floating gate (FG). The SG is exposed to fluid, the CG is independently driven, and the FG is capable of storing charge Q(FG) of either polarity. Asymmetric capacitive coupling between the CG and SG to FG results in intrinsic amplification of the measured surface potential shifts and influences the FG charge injection mechanism. This modified SG surface condition was monitored through transient recordings of the output current, performed under alternate positive and negative CG pulses. Transient recordings revealed a hysteresis where the current was enhanced under negative pulsing and reduced after positive pulsing. This hysteresis effect is similar to that observed with EOS capacitors, suggesting a field-dependent surface charge regulation mechanism at play. At high CG biases, nonvolatile charge Q(FG) tunneling into the FG occurs, which creates a larger field and tunes the pH response and the point of zero charge. This mechanism gives rise to surface programmability. In this paper we describe the operational principles, tunneling mechanism, and role of electrolyte composition under field modulation. The experimental findings are then modeled by a Poisson-Boltzmann formulation with surface pH regulation. We find that surface ionization constants play a dominant role in determining the pH tuning effect. In the following paper [K. Jayant et al., Phys. Rev. E 88, 012802 (2013)] we extend the dual-gate operation to molecular sensing and demonstrate the use of Q(FG) to achieve manipulation of surface-adsorbed DNA.

Self-Amplified Dual Gate Charge Trap Flash Memory for Low-Voltage Operation

We propose a self-amplified charge trap Flash memory using the dual-gate (DG) mode operation based on the capacitive coupling between the front-gate and back-gate as a promising next-generation nonvolatile memory. It is found that the coupling ratio and memory window strongly depend on the thickness of the buried oxide (BOX) layer in the silicon-on-insulator (SOI) substrate. As the BOX thickness of the SOI substrate increases, the coupling ratio and memory window of Flash memory cells increase. The DG mode can obtain a larger memory window, reduced operation voltage, and improved reliability compared with the conventional single-gate mode operation.

Enhanced Sensing Properties by Dual-Gate Ion-Sensitive Field-Effect Transistor Using the Solution-Processed Al2O3 Sensing Membranes

The sensitivity of conventional ion-sensitive field-effect transistors (ISFETs) is limited to 59 mV/pH, which is the maximum value in electrochemical potential according to the Nernst equation. Here, the silicon-on-insulator (SOI) based dual-gate (DG) ISFETs with SiO2/Al2O3 (OA) using solution based process was evaluated to obtain higher pH sensitivity. The device exhibited a significantly enhanced pH sensitivity of 407.3 mV/pH for the DG operation by capacitive coupling between top and bottom gate oxide. Therefore, the SOI-based ISFETs using solution process and the DG monitoring method are very promising to biological sensors application in terms of high performance and large process area.

Sensitivity enhancement of amorphous InGaZnO thin film transistor based extended gate field-effect transistors with dual-gate operation

Amorphous indium–gallium zinc oxide (a-IGZO) based TiO2 extended gate field-effect transistors (EGFETs) with a high pH sensitivity of 129.1mV/pH beyond the Nernst response limit were realized by the dual gate operation mode. The capacitive coupling between the front and bottom gate dielectric for the DG operation greatly improved its sensitivity as well as its chemical stability. The developed high performance pH sensor was rooted in outstanding electrical characteristics of an a-IGZO thin film transistor with an on/off current ratio of 3.7×107, a subthreshold swing of 86mV/dec, and a field-effect mobility of 17.62cm2/Vs.

Improved sensing performance of polycrystalline-silicon based dual-gate ion-sensitive field-effect transistors using high-k stacking engineered sensing membrane

Improved sensing performance, larger pH sensitivity that breaches the Nernst response limit with excellent stability, was realized on polycrystalline silicon based dual-gate (DG) ion-sensitive field-effect transistors. The capacitive coupling between the top and bottom gate oxides for a DG operation amplified its sensitivity to as high as 325.8 mV/pH. In particular, the SiO2/HfO2/Al2O3 (OHA) layer, proposed as an engineered sensing membrane, significantly reinforced the sensing margin of devices as well as the chemical stability for long-term use. The sensing characteristics of the OHA and conventional SiO2 layer were evaluated for single gate and DG operation modes, respectively.

Double layer capacitance measured by organic field effect transistor operated in water

Pentacene ultra thin film transistors were exposed to water and operated with a conventional silicon/silicon oxide bottom gate and an electrolyte top gate controlled by a working electrode. The transistors are highly sensible (µV) to the electrochemical potential of the aqueous electrolyte. We show that dual gate operation permits the measurement of the double layer capacitance, CDL = 14.6 µF/cm2. The device exhibits a fast (4.6 ms) and stable response, without bias stress as opposed to conventional bottom gate operations, when controlled with the electrolyte gate. These features make the device a promising candidate for potentiometric transducers required for non-invasive electrophysiology.

Fabrication of high-performance fully depleted silicon-on-insulator based dual-gate ion-sensitive field-effect transistor beyond the Nernstian limit

High-performance dual-gate (DG) ion-sensitive field-effect transistors (ISFETs) beyond the Nernstian limit of 59 mV/pH were realized using the fully depleted (FD) silicon-on-insulator (SOI) substrate. The FD SOI-based DG ISFET exhibited a significantly enhanced pH sensitivity of 379.2 mV/pH for DG operation amplified by capacitive coupling, while it exhibited a relatively poor sensitivity of 47.9 mV/pH for single-gate (SG) operation. Meanwhile, the non-ideal effects for long-term use slightly increased by the DG operation compared to the SG operation. Therefore, the FD SOI-based DG ISFETs compatible with the complementary metal-oxide-semiconductor process are considered to be very promising bio-chemical sensors.

Self-aligned lateral dual-gate suspended-body single-walled carbon nanotube field-effect transistors

Self-aligned lateral dual-gate suspended-body single-walled carbon nanotube (CNT) field-effect transistors (CNFETs) have been demonstrated. A nano-precision assembly method using resist-assisted ac-dielectrophoresis is applied. Superior I-V characteristics controlled by two independent lateral gates spaced sub-100 nm away from the CNT body are experimentally observed and studied. The dual-gate operation mode effectively boosts the device performance: 34% smaller subthreshold slope, three times larger on-current, and four times higher transconductance. The proposed dual-gate suspended-body CNFETs hold promise for bottom-up fabrication of advanced complementary metal-oxide-semiconductor circuits and nano-electro-mechanical systems devices, such as tunable/switchable resonators for sensing and radio-frequency applications.

Dual-Gate Operation of a Carbon Nanotube Field Effect Transistor with a Local Gate Electrode

Dual-Gate Operation of a Carbon Nanotube Field Effect Transistor with a Local Gate Electrode

InAs/AlSb dual-gate HFETs

We report the first implementation of InAs/AlSb dual-gate (DG) HFETs. The devices were fabricated by conventional optical lithography and consist of two electrically distinct 1-μm gates, with a 1-μm intergate separation. The DG-HFETs feature well-behaved, kink-free drain characteristics, and exhibit both high transconductance and low output conductance. We find that DG operation significantly reduces the short-channel effects that have so far plagued InAs/AlSb devices, and increases the maximum allowable drain bias. We estimate that cutoff frequencies as high as 30 GHz-μm may be possible for such devices based on simple equivalent circuit models and previously published experimental data on single-gate InAs/AlSb HFETs.

Comments, with reply, on 'Dual-gate operation and volume inversion in n-channel SOI MOSFETs' by S. Venkatesan et al

For original paper see ibid., vol.13, no.1, pp.44-6 (Jan. 1992). The commenter disagrees with the suggestion by S. Venkatesan, et al. that dual-channel volume inverted devices do not offer significant current-enhancement advantages, other than that expected from the second channel, over the conventional single-channel devices for silicon thicknesses in the 0.1- mu m range. The commenter argues that this suggestion is in contradiction with previous demonstrations and with recent results that experimentally show the advantages of volume inversion. In replying, Venkatesan, et al., maintain that, while volume inversion could cause drain current enhancements in the near threshold region, it does not significantly affect the device characteristics in the strong inversion regime.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Dual-gate operation and volume inversion in n-channel SOI MOSFET's

The effects of volume inversion in thin-film short-channel SOI MOSFETs and the efficacy of dual-gate operation in enhancing their device performance have been analyzed using two-dimensional device simulations and one-dimensional analytical computations. The analyses have been restricted to the strong inversion regime, which is the practically useful region of operation of the SOI MOSFETs. In this region, the analyses suggest that when compared at constant V/sub G/-V/sub T/ values, the dual-channel volume inverted devices do not offer significant current-enhancement advantage, other than that expected from the second channel, over the conventional single-channel devices for silicon thicknesses in the 0.1- mu m range.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Adaptation of the charge pumping technique to gated p-i-n diodes fabricated on silicon on insulator

The charge pumping technique was applied to MOS p-i-n diodes and used to characterize silicon-on-insulator films synthesized by oxygen implantation. The flatband and threshold voltages, effective channel length, capture cross sections, and densities of traps at the front and back interfaces were extracted. The parameters of the charge pumping phenomenon were systematically studied, and the ranges of validity are discussed. A parasitic component, due to an excess recombination of mobile carriers, occurs for very short transients during both the rise and fall of the gate pulse. It is demonstrated that the carrier reservoirs situated at the back interface play a significant role. Other specific features related to the dual-gate operation and interface coupling in silicon-on-insulator films are presented. An improved model is developed for the interpretation of the interface state profile in the energy gap.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Gigabit-per-second dual-gate MESFET switching and multiplexer operation for high-speed fiber-optic systems

The operation of dual-gate GaAs MESFET's in gigabit-per-second switching applications for high-speed fiber-optic systems is investigated, and a full nonlinear modeling procedure is presented for general switching simulations. The model is characterized via a new and efficient technique which only requires two-port s -parameter measurements to determine the nonlinear element variations. Circuit simulations implemented on program SPICE 2 have been applied to evaluate the transient switching response of dual-gate MESFET's in several circuits involving 1-Gbit/s pulse conversion and synchronization, pulse-width reduction and 2-Gbit/s multiplexing, and results show good agreement between predicted and experimental switching waveforms.