Impacts of Independent Dual-Gate Operation on Reliability of Nanosheet Junctionless Thin-Film Transistor

Abstract

In this work, impacts of the independent dual-gate (IDG) operation on performance and reliability of the polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) with a nanosheet channel (~4 nm) are investigated. Compared to the single-gate (SG) operation, the JL-TFT with tied dual gate (DG) operation times maximum transconductance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${G}_{m\_{}{\text {max}}}$ </tex-math></inline-formula> ) improvement and 3.3 times driving current enhancement. The tied DG operation also exhibits better gate bias stress immunity than the SG operation although the tied DG stress causes more serious damages to the JL-TFT than the SG stress. As for the independent back gate (BG) voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> ) operation mode, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> can provide a wide threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> ) tuning range ~2 V when the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> is modulated from 0 to −4 V. The negative <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> bias stress would induce electron injection from the BG, resulting in positive <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shift. Because the positive top gate voltage stress exhibits more serious electrical degradation than the negative <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> stress, using <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> to modulate the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> of the JL-TFT will cause a slightly more serious reliability issue. The results show the feasibility of using independent <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> to adjust the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> of the JL-TFTs to meet the multiple- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> requirement of advanced integrated circuits.