Dual-gate CMOS Research Articles

A new pressure microsensor based on dual-gate graphene field-effect transistor with a vertically movable top-gate: Proposal, analysis, and optimization

The combination of modern electronic devices and nanoelectromechanical systems (NEMS) has given new impulses to the development of sensors and biosensors. A new pressure microsensor based on graphene field-effect transistor (GFET) endowed with dual-gate design is proposed herein. The movable top-gate concept is used as sensing principle to detect the pressure-induced nanoscale displacement. A compact GFET drain-current model based on drift-diffusion carrier transport and field-effect principle is employed for the performance assessment of the proposed pressure microsensor. The investigation includes the top-gate and dual-gate configuration, transfer characteristic behavior, sensitivity analysis, operating regime, and the impact of gates' biases on the microsensor sensitivity. The performance analysis reveals that the dual-gate GFET design outperforms the top-gated GFET in terms of sensitivity. In addition, the high back-gate voltage and the low drain-source voltage have been found useful in improving the sensitivity of the DG GFET-based pressure sensor. Moreover, a metaheuristic optimization technique based on genetic algorithm (GA) has been adopted to find the optimal sensor parameters values that lead to the best sensitivity performance. The merits of the proposed dual-gate GFET-based pressure microsensor, namely small-size, high-sensitivity, graphene cost, and CMOS compatibility, make it a promising candidate for high-performance pressure sensing applications.

65-nm CMOS Dual-Gate Device for Ka-Band Broadband Low-Noise Amplifier and High-Accuracy Quadrature Voltage-Controlled Oscillator

Design and analysis of a two-stage low-noise amplifier (LNA) and a bottom-series coupled quadrature voltage-controlled oscillator (QVCO) using a 65-nm CMOS dual-gate device are present in this paper. By using the proposed dual-gate device, the parasitic capacitance and the effective substrate resistance can be reduced. Moreover, the 3-dB cutoff frequency can be extended due to the reduction of the Miller effect. The bandwidth of the dual-gate LNA is investigated to compare with the conventional cascode configuration. Besides, the operation principle of the quadrature signal generation using the dual-gate device is also presented for the QVCO design. The two-stage dual-gate LNA demonstrates a flat 3-dB bandwidth of 7.3 GHz from 19.4 to 26.7 GHz and a maximum gain of 18.9 dB. At 24 GHz, the measured minimum noise figure is 4.7 dB, and the measured output third-order intercept point <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$({\rm OIP}_{3})$</tex></formula> is 11 dBm. The dual-gate QVCO exhibits an oscillation frequency of up to 25.3 GHz, a phase noise of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex></formula> 109 dBc/Hz at 1-MHz offset frequency, an amplitude error of 0.16 dB, and a phase error of 0.8 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}$</tex></formula> . The proposed dual-gate CMOS device is very suitable for the linear and nonlinear circuit designs above 20 GHz, especially for millimeter-wave applications due to its high speed and compact area.

A Noise-Shaped Buck DC–DC Converter With Improved Light-Load Efficiency and Fast Transient Response

A noise-shaped synchronous buck dc-dc converter based on a third-order active-passive continuous-time sigma-delta modulator is presented. Detailed system modeling and loop design methodology are discussed. A dual-mode compensator is proposed to achieve the loop stability over a wide load range. The light-load efficiency is improved by the proposed dynamic width control and sigma-delta pulse-skip mode techniques. In order to get a fast transient response, the linear-nonlinear control is adopted. Moreover, an on-chip soft-start circuit is proposed to save the system cost. The proposed converter has been fabricated using Chartered 0.35- μm 2P4M dual-gate mixed-signal CMOS process. Experimental results show that the converter effectively suppresses the switching harmonics at both continuous conduction mode and discontinuous conduction mode. Compared with the conventional pulsewidth modulation operation, the first harmonic peak has been reduced by -35 dB. The converter achieves a peak efficiency of 92% at 200 mA, and a light-load efficiency of 78% at 5 mA. With the load current skipping between 50 and 450 mA, the maximum output overshoot voltage is 87 mV, and the recovery time is below 12 μs. The start-up time for the output voltage is 160 μs. By configuring the soft-start circuit, this time can be prolonged to 680 μs. The area of the whole chip is 1.4 mm2.

A 0.18-$\mu{\hbox {m}}$ Dual-Gate CMOS Device Modeling and Applications for RF Cascode Circuits

A merged-diffusion dual-gate CMOS device model is presented in this paper. The proposed large-signal model consists of two intrinsic BSIM3v3 nonlinear models and parasitic components. The parasitic elements, including the substrate networks, the distributed resistances, and the inductances, are extracted from the measured S-parameters. In order to verify the model accuracy, a cascode configuration with the proposed dual-gate device is employed in a low-noise amplifier. The dual-gate model is also evaluated with power sweep and load-pull measurements. In addition, a doubly balanced dual-gate mixer is successfully demonstrated using the proposed model. The measured results agree with the simulated results using the proposed device model for both linear and nonlinear applications. The advanced large-signal dual-gate CMOS model can be further used as an RF sub-circuit cell for simplifying the design procedure.

Cleaning and Strip Requirement for Metal Gate Based CMOS Integration

This paper describes the basic process steps involved in the dual metal gate CMOS integration. It focuses on the differences between a dual metal dual dielectric and single metal dual dielectric integration. The focus is on basic process steps involved in both process flows, but device data are also presented to illustrate the processes.

Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi- Vt CMOS application

Dual metal gate CMOS FinFETs have been integrated successfully by the Ta/Mo interdiffusion technology. For the first time, low- V t CMOS FinFETs representing on-current enhancement and high- V t CMOS FinFETs reducing stand-by power dramatically, namely multi- V t CMOS FinFETs, are demonstrated by selecting Ta/Mo gates for n or pMOS FinFETs with non-doped fin channels. The dual metal gate FinFET SRAM with a low- V t configuration is demonstrated with excellent noise margins at a reduced supply voltage.

An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8:4 Multiplexed Data-Transfer Scheme

Three circuit techniques for an 8.1-ns column-access 1.6-Gb/s/pin 512-Mb DDR3 SDRAM using 90-nm dual-gate CMOS technology were developed. First, an 8:4 multiplexed data-transfer scheme, which operates in a quasi-4-bit prefetch mode, achieves a 3.17-ns reduction in column-access time, i.e., from 11.3 to 8.13 ns. Second, a dual-clock latency counter reduces standby power by 22% and cycle time from 1.7 to 1.2 ns. Third, a multiple-ODT-merged output buffer enables selection of five effective-resistance values Rtt (20, 30, 40, 60, and 120 Omega) without increasing I/O capacitance. Based on these techniques, 1.6-Gb/s/pin operation with a 1.36-V power supply and a column latency of 7 was accomplished

Challenges in Dual Workfunction Metal Gate CMOS Integration

Technical challenges for various integration schemes including gate first dual metal process, fully silicided gate and replacement gate are discussed. Implementation of dual workfunction metal gate CMOS integration is feasible, but needs more systematic reliability assessment.

CMOS Integration Issues with High-K/Metal Gate Stack

This paper reviews some of the integration challenges that high-K/metal gate stack technology is facing. This includes thermal stability of high-K against crystallization, phase separation, and interfacial reaction with underlying Si, charges/traps in high-K as well as at interfaces, channel carrier mobility degradation, EOT control and scaling, work function control for dual-gate CMOS integration, and gate stack reliability. The engineering of the high-K/Si as well as metal/high-K interfaces is identified as the most important factor for achieving EOT<<1nm with good performance and reliability.

A 14-bit Digitally Self-Calibrated Pipelined ADC With Adaptive Bias Optimization for Arbitrary Speeds Up to 40 MS/s

This paper presents a 14-bit digitally self-calibrated pipelined analog-to-digital converter (ADC) featuring adaptive bias optimization. Adaptive bias optimization controls the bias currents of the amplifiers in the ADC to the minimum amount required, depending on the sampling speed, environment temperature, and power-supply voltage, as well as the variations in chip fabrication. It utilizes information from the digital calibration process and does not require additional analog circuits. The prototype ADC occupies an area of 0.5/spl times/2.3 mm/sup 2/ in a 0.18-/spl mu/m dual-gate CMOS technology; with a power supply of 2.8 V, it consumes 19.2, 33.7, 50.5, and 72.8 mW when operating at 10, 20, 30, and 40 MS/s, respectively. The peak differential nonlinearity (DNL) is less than 0.5 least significant bit (LSB) for all the sampling speeds with temperature variation up to 80/spl deg/C. When operated at 20 MS/s with 1-MHz input, the ADC achieves 72.1-dB SNR and 71.1-dB SNDR.

Substrate and process dependence of gate oxide reliability of 0.18μm dual gate CMOS process

V-ramp method was used to evaluate gate oxide reliability of 0.18μm dual gate CMOS process. Charge of breakdown (Qbd) and voltage of breakdown (Vbd) of gate oxide with n-type substrate and p-type substrate were extracted. It was found that for low voltage (thin oxide) gate oxide device the Qbd of gate oxide of n-type substrate and p-type substrate are almost the same, but for high voltage (thick oxide) gate oxide device the Qbd of n-type substrate and p-type substrate have a big difference. At the same time, Qbd of gate oxide with p-substrate is bigger than that of gate oxide with n-substrate. The difference of Qbd of thin gate oxide and thick gate oxide can be attributed to lithographic damage to the interface of poly-silicon gate and thick gate oxide. There is a big difference between the Weibull slopes of charge of breakdown of thin oxide and thick oxide. For the voltage of breakdown, Similar difference between n-substrate and p-substrate gate oxide was also observed. However, there is no big difference between the Weibull slopes of voltage of breakdown of thin oxide and thick oxide.

Continuous and Precise Work Function Adjustment for Integratable Dual Metal Gate CMOS Technology Using Hf–Mo Binary Alloys

We demonstrate for the first time a continuous and almost linear work function adjustment between 3.93 and 4.93eV using Hf/sub x/Mo/sub (1-x)/ binary alloys deposited by co-sputtering. In view of the process integration, dual work function metal gate technology using Mo and Hf/sub x/Mo/sub (1-x)/ formed by metal intermixing was proposed. Work function values were verified to be a function of the thickness ratio and accurate work function adjustment can be possible. Furthermore, one can be allowed to get around the thermal stability issue by choosing an appropriate total metal thickness corresponding to the thermal budget subsequent to gate deposition, since the thermal budget required for metal intermixing depends on the total metal thickness.

Work Function Tuning of Fully Silicided NiSi Metal Gates Using a TiN Capping Layer

This paper investigates a new way of tuning the work function of fully silicided (FUSI) NiSi metal gates for dual-gate CMOS using a TiN capping layer on Ni to control the poly-Si dopant distribution during FUSI formation. In addition, by comparing the work function change of NiSi FUSI with and without TiN capping, we provide clear evidence that dopants at the gate electrode and dielectric interface are responsible for the work function change. The TiN capping layer causes no degradation to the underlying gate dielectric in terms of fixed-oxide charge, gate leakage current, and time-dependent dielectric breakdown characteristics.

Dual work function metal gates using full nickel silicidation of doped poly-Si

This paper investigates the work function adjustment on fully silicided (FUSI) NiSi metal gates for dual-gate CMOS, and how it is effected by the poly-Si dopants. By comparing FUSI on As-, B-, and undoped poly-Si using the same p-Si substrates, it is shown that both As and B influence the work function of NiSi FUSI gate significantly, with As showing more effects than B possibly due to more As pile-up at the NiSi-SiO/sub 2/ interface. No degradations on the underlying gate dielectrics are observed in terms of interface state density (D/sub it/), fixed oxide charges, leakage current, and breakdown voltage, suggesting that NiSi FUSI is compatible with dual-gate CMOS processing.

An integratable dual metal gate CMOS process using an ultrathin aluminum nitride buffer layer

We propose and demonstrate a novel approach for dual metal gate CMOS process integration through the use of a very thin aluminum nitride (AlN/sub x/) buffer layer between metal and gate oxide. This buffer layer prevents the gate oxide from being exposed to a metal etching process which potentially causes oxide thinning and damage. Subsequent annealing consumes the very thin AlN/sub x/ layer and converts it into a new metal alloy film by reacting with gate metals, resulting in no increase in EOT due to this buffer layer. The work function of the original gate metal is also modified as a result of its reaction with AlN/sub x/, making this approach extremely attractive for engineering the work function for dual metal gate CMOS applications.

Performance advantage of schottky source/drain in ultrathin-body silicon-on-insulator and dual-gate cmos

Here, for the first time, advanced simulation models are used to investigate the performance advantage of Schottky source/drain ultrathin-silicon technologies at a 25-nm gate length target. Schottky and doped source/drain MOSFETs were optimized and compared using a novel benchmark. Mixed-mode simulations of optimized devices in a two-stage NAND chain show an approximate 45% speed advantage of Schottky source/drain for one set of parameter choices. Contact requirements for Schottky source/drain, and for doped source/drain relative to ITRS targets through 2016, are discussed.

A 0.18-μm RF SiGe BiCMOS technology with collector-epi-free double-poly self-aligned HBTs

This paper describes an RF SiGe BiCMOS technology based on a standard 0.18-/spl mu/m CMOS process. This technology has the following key points: 1) A double-poly self-aligned SiGe-HBT is produced by adding a four-mask process to the CMOS process flow-this HBT has an SiGe epitaxial base selectively grown on an epi-free collector; 2) two-step annealing of CMOS source/drain/gate activation is utilized to solve the thermal budget tradeoff between SiGe-HBTs and CMOS; and 3) a robust Ge profile design is studied to improve the thermal stability of the SiGe-base/Si-collector junction. This process yields 73-GHz f/sub T/, 61-GHz f/sub max/ SiGe HBTs without compromising 0.18-/spl mu/m p/sup +//n/sup +/ dual-gate CMOS characteristics.

Dopant diffusion control by adding carbon into Si and SiGe: principles and device application

The incorporation of low concentrations of carbon (<10 20 cm −3) into the SiGe region of a heterojunction bipolar transistor (HBT) can significantly suppress boron outdiffusion caused by subsequent processing steps. This effect can be described by coupled diffusion of carbon atoms and Si point defects. We discuss the increase in performance and process margins in SiGe heterojunction bipolar technology by adding carbon. SiGe:C HBTs demonstrate excellent static parameters, exceeding the performance of state-of-the-art SiGe HBTs. Carbon also enhances the high frequency performance, because it allows one to use a high B doping level in a very thin SiGe base layer without outdiffusion from SiGe, even if applying post-epitaxial implants and anneals. Finally, we demonstrate the first modular integration of SiGe:C HBTs into a 0.25 μm, epi-free, dual-gate CMOS platform.

Zr Oxide Based Gate Dielectrics with Equivalent SiO2 Thickness of Less than 1.0 nm and Device Integration with Pt Gate Electrode

ABSTRACTZrO2 films are investigated as an alternative to SiO2 gate dielectric below 1.5nm. A maximum accumulation capacitance ∼35 fF/μm2 with a leakage current of less than 0.1 A/cm2 has been achieved for a 3 nm Zr-O film, suggesting that ZrO2 can be scaled to below an equivalent oxide thickness of 0.5 nm. Al and Si doping is also investigated to reduce leakage currents and to increase the crystallization temperature of the film. Submicron MOSFETs with TiN or Pt gate electrodes have been fabricated with these gate dielectrics with excellent characteristics, demonstrating the feasibility of CMOS process integration. In particular, Pt damascene gate PMOS is shown to have the proper threshold voltage for dual metal gate CMOS application.

Doubly balanced dual-gate CMOS mixer

The operation, biasing, and measured results of a CMOS doubly balanced dual-gate downconversion mixer are presented. Measurements show, with a radio-frequency input of 1.9 GHz and an intermediate-frequency output of 250 MHz, that the mixer has a conversion gain of 0 dB, an input-referred third-order intercept point of +2 dBm, and a single-sideband noise figure of 13.6 dB while requiring +5 dBm of local-oscillator power and consuming 10.2 mA from a 3 V power supply.