Abstract

A noise-shaped synchronous buck dc-dc converter based on a third-order active-passive continuous-time sigma-delta modulator is presented. Detailed system modeling and loop design methodology are discussed. A dual-mode compensator is proposed to achieve the loop stability over a wide load range. The light-load efficiency is improved by the proposed dynamic width control and sigma-delta pulse-skip mode techniques. In order to get a fast transient response, the linear-nonlinear control is adopted. Moreover, an on-chip soft-start circuit is proposed to save the system cost. The proposed converter has been fabricated using Chartered 0.35- μm 2P4M dual-gate mixed-signal CMOS process. Experimental results show that the converter effectively suppresses the switching harmonics at both continuous conduction mode and discontinuous conduction mode. Compared with the conventional pulsewidth modulation operation, the first harmonic peak has been reduced by -35 dB. The converter achieves a peak efficiency of 92% at 200 mA, and a light-load efficiency of 78% at 5 mA. With the load current skipping between 50 and 450 mA, the maximum output overshoot voltage is 87 mV, and the recovery time is below 12 μs. The start-up time for the output voltage is 160 μs. By configuring the soft-start circuit, this time can be prolonged to 680 μs. The area of the whole chip is 1.4 mm2.

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