Dropout Voltage Research Articles

A Study of High Transient Response Low Dropout Linear Regulator Chips

Abstract. With the rapid development of the microelectronics industry in the world, electronic products are being updated more and more quickly. This has created a growing large market demand for power management chips. Low drop-out linear regulators have become one of the most widely used types of power management chips due to their advantages of high stability, low drop-out voltage, and fast response. This paper is a data collection study and comparison of improvement methods based on high transient response low drop-out linear regulators. It describes the basic principles of LDOs as well as the principles, advantages and disadvantages of different improvement methods. It was found that the method of shortening the overshoot and undershoot durations by constructing transient enhancement circuits was the best in terms of performance among the following research methods. The stability of capacitor-less LDO is harder to control. Using compensation circuits to improve stability will increase circuit complexity. The capacitor-coupled current mirror method has a longer startup time, because it takes some time for it to reach homeostasis. The high complexity and energy consumption of the dual feedback loop structure makes the circuit costly.

A transient-enhanced output-capacitorless LDO regulator with non-inverting pull–push gain stage

A novel non-inverting pull–push gain stage output-capacitorless low-dropout regulator (OCL-LDO) is introduced, designed specifically for power management of system-on-chip (SoC). The incorporation of an innovative non-inverting gain stage (NIGS) serves to shift the non-dominant parasitic poles to higher frequencies, thereby enhancing the overall stability of the system. The proposed pull-push configuration markedly improves the slew rate limitation at the gate of the power transistor. Post-layout simulation outcomes, corroborated through a 180-nm CMOS fabrication process, indicate that the proposed LDO regulator maintains stability across a wide range of loading currents, from 0 mA to 100 mA, with a Miller compensation capacitance of only 3.5 pF. The circuit operates with a quiescent current of 143 μA when powered by a 1.5 V single supply. The LDO regulator boasts a dropout voltage of 300 mV, enabling it to deliver up to 100 mA of load current. Simulation results show that the undershoot voltage is only 63.7 mV when the load current jumps from 0 to 100 mA with edge of 100 ns, while employing a 100 pF capacitance load. The recovery time to return to equilibrium post this abrupt change is approximately 0.15 μs. The proposed OCL-LDO regulator exhibits a substantial enhancement in transient response compared to its predecessors, alongside a harmonized balance between line regulation and load regulation performance parameters.

A Transient-Enhanced Capacitorless LDO Design

Abstract This paper introduces a capacitor-less low drop-out voltage regulator (LDO) designed for fast transient response. Traditional capacitor-less LDOs often suffer from suboptimal transient responses, leading to unstable outputs during load transitions. To address this challenge, the circuit employs voltage rise and fall suppression circuits to mitigate voltage spikes. It utilizes slew rate enhancement techniques to improve the transient response characteristics of the LDO. Miller compensation is applied to achieve phase margin compensation with a smaller capacitor area. Simulation outcomes indicate that within the voltage range of 2.2 V to 3.3 V, the circuit provides a stable output voltage of 1.8 V while accommodating a peak load current of 100 mA. When the load current undergoes a step change between 1 mA and 100 mA, the transient enhancement circuit reduces the undershoot of the output voltage by 58 mV, a decrease of 39%, with a response time of 1.13 μs. The overshoot amplitude is reduced by 212 mV, a decrease of 70.6%, with a response time of 1.21 μs.

Phenothiazine Derivatives as Small-Molecule Organic Cathodes with Adjustable Dropout Voltage and Cycle Performance.

Compared with conventional inorganic materials, organic electrodes are competitive candidates for secondary battery cathodes due to their resourcefulness, environmental friendliness, and cost-effectiveness. Much effort is devoted at the level of chemical structure, while ignoring the impact of molecular aggregation on battery behavior. Herein, this work designs a series of organic molecules with two electrochemically active phenothiazine groups linked by different lengths of alkyl chain to regulate molecular symmetry and crystallinity. The results emphasize the equally important role of molecular aggregation and chemical structure for battery performance. Among them, 2PTZ-C7H14|Li cell exhibits the most impressive cycle and rate performance. At the high rate of 50 C, it can still deliver a capacity of 63.4 mA h g-1 and 74.5% capacity retention after 10000 cycles. Besides, the dropout voltage of 2PTZ-C9H18|Li cell is only 52 mV, which is among the lowest reported for lithium-organic batteries to the best of the author's knowledge.

A 1.8 V, 10 mA low dropout voltage regulator for IoT application in 90 nm CMOS technology

A complementary metal-oxide-semiconductor CMOS low dropout voltage regulator (LDO) design flow using 90 nm CMOS technology is described and simulated in this paper. The circuit consists of an analogue LDO with using PMOS pass device, an error amplifier, a bandgap voltage, a biasing circuit, a feedback resistive network sized to have the desired closed loop gain. This LDO was designed to maintain stable voltage at 1.8 V and 10 mA of current output in low resistive load. The LDO regulator achieves 105 uA quiescent current, -47 PSRR@13 KHz noise frequency. The final design occupies approximately 0.05 mm<sup>2</sup>. The results were satisfying and make the designed circuit suitable for IoT application.

High-precision Low-power Low-temperature Drift Dropout Voltage Cancellation Oscillator

As electronic products continue to develop, the requirements for the accuracy of integrated circuits continue to increase. Oscillators play a more important role in integrated circuits, and higher requirements are placed on the power consumption as well as the accuracy of oscillators. In this paper, a high-precision and low-power consumption RC oscillator is designed. The oscillator in this paper consists of a bias module and a capacitor charging and discharging module and provides bias current and voltage with temperature coefficient through bandgap to reduce the change of oscillator operating frequency caused by the increase of ambient temperature in traditional oscillators, which improves the oscillator operating state under different temperatures and the accuracy of the oscillator. The single comparator oscillator structure is also designed to effectively eliminate the effect of the dropout voltage on the oscillation period. The oscillator is simulated by using the MGN 0.18 μm process.

A 1-A Switching LDO With 40-mV Dropout Voltage and Fast DVS

This brief presents a 1-A fully-integrated switching LDO for digital loads. By using 4-phase 200-MHz pulse-width modulation (PWM), it can significantly reduce the output ripple and allow using a smaller output capacitor. Distinctive from the prior dual-loop structure, we adopt a single feedback loop with a wide bandwidth error amplifier (EA) using a quasi-Type-III compensation to improve the dynamic voltage scaling (DVS) rate and to reduce the transient recovery time. Meanwhile, compared with the prior stacked power transistor architecture, the single-PMOS with auxiliary constant current (ACC) control can reduce by 4-fold the power transistor size, and decreases the driver current by at least 2.5 times. Fabricated in 28-nm bulk CMOS, the proposed LDO measures a 1-A load capability with a 40-mV dropout voltage. Moreover, the measured load regulation is 2.2 mV/A, and the line regulation is 1.8 mV/V. In addition, the regulator obtains a fast DVS speed of 4V/μs and a fast load transient recovery time of <50ns.

A Low Power Low Inrush Current LDO with Different Techniques for PSR and Stability Improvement

One of the most popular power management regulators is the low drop-out voltage regulator (LDO). LDOs have different specifications such as the power supply rejection (PSR) over different frequencies, stability over different load ranges, inrush current spike flows through the input supply, and power consumption. In this work, we present a low power low inrush current LDO design with different techniques for PSR and stability improvement across different frequencies. The LDO presented in this work is a low-power and small area LDO but achieves a high PSR over a wide range of frequencies. The LDO is designed in 65 nm CMOS technology and achieves a PSR better than 80 dB up to 30 MHz for an output load current of 25 mA using an output load capacitor of 4 µF. The design can be used in capless/capped LDOs with wide load current ranges as high as 200 mA and load capacitor range from 1 nF to 12 µF with inrush current improvement by more than 2×. The presented LDO consumes a zero-load quiescent current of 10 µA and its area of 180 µm × 180 µm.

A CAFVF-based output-capacitor-less LDO with PSRR improvement by feed forward and negative capacitance

This paper presents an output-capacitor-less LDO regulator that is implemented in a 0.18μm CMOS process. It is based on an improved cascode flipped voltage follower that uses two buffer stages to improve loop stability and load current. The feed forward PSRR improvement technique and the equivalent negative capacitance PSRR improvement technique are proposed to improve the power supply rejection ratio (PSRR) performance up to 24 dB at 10 kHz and 38 dB at 100 kHz, respectively. The quiescent current is 27.7 μA, enabling a maximum load current of 50 mA with a dropout voltage of 200 mV. It also achieves excellent line regulation of 0.675 mV/V and load regulation of 8.2 μV/mA.

Low-Cost Structural Monitoring of Analog Circuits for Secure and Reliable Operation

The need for digital calibration due to large variations in fine-geometry processes as well as the need for performance locking mechanisms to prevent IC piracy have resulted in the prevalent use of digital assistance for analog circuits. In order to ensure the secure and reliable operation of the system, the performance of the analog circuits needs to be monitored in the field with robust, low-cost methods. In this paper, we propose a method reliant on monitoring simple invariants for detecting performance degradation of digitally-assisted analog circuits. We demonstrate the proposed method on two circuits: a low drop-out voltage regulator (LDO) and an active low-pass filter. Extensive Monte-Carlo simulations confirm that the proposed method detects deviations in performance due to tampering.

Made to Measure Squaramide COF Cathode for Zinc Dual‐Ion Battery with Enriched Storage via Redox Electrolyte

AbstractAqueous rechargeable batteries are promising grid‐scale energy storage devices because of their affordability, operational safety, and environmental benignity. Among these, Zn‐ion batteries (ZIBs) have unfolded new horizons. Designing superior cathodes for ZIBs is crucial. Covalent organic frameworks (COFs) can be made redox active with a high storage surface. Here, for the first time, a chelating COF with redox‐active ZnI2 in a ZnSO4(aq) electrolyte is combined. Including iodide harvests an approximately threefold enhancement in capacity from 208 to 690 mAh g−1 at 1.5 A g−1, the highest among all the COF‐derived ZIBs. Remarkably, a charge–discharge curve at 1.3 V exhibits very limited dropout voltage and super‐flat platform, with a remarkable capacity of 600 mAh g−1 at 5 A g−1 stable up to 6000 cycles, confirming that the polyiodide generation and storage are sustainable. The COF's dual‐ion storage (Zn2+ and polyidode) delivers a ZIB with the highest energy density. Spectro‐electrochemical measurements coupled with X‐ray photoelectron spectroscopy unambiguously unveil the existence of multiple polyiodide species, with I3− and IO3− ions as the prominent species. The latter gets reduced at the COF electrode under an applied potential, leaving I3− as the major species stored on the COF. The prospect of COF‐polyiodide(aq) is a windfall for metal‐ion batteries.

Programmable 1 A ultra-low dropout LDO regulator for high-resolution camera sensors

In this article, design and realization of a high-performance linear low dropout regulator (LDO) capable of supplying 1 A of output current, designed and fabricated in 180 nm BCD technology of STMicroelectronics company, is described. The main purpose of this device is providing a stable output voltage for supplying high-resolution sensors of cameras in cellphones. The LDO is equipped with a big N-channel power transistor allowing an ultra-low dropout voltage around 50 mV at the maximal load current of 1 A even with a very low level of the output voltage of only 0.4 V. These features make the device suitable as a block following buck switching converters. Emphasis has been laid on assuring 1% accuracy of the output voltage across full temperature range and line and load conditions, very low quiescent current around 32 μA, necessary for battery powered applications such as cellphones, good transient response and a high power supply rejection ratio (PSRR) of more than 85 dB at 1 kHz. This combination of high-level parameters stands for an extraordinary device. The proposed LDO is a programmable device which means that the output voltage (up to 100 voltage versions in total) and other functions can be set via post-package electrical trimming. Last but not least, an efficient design for testability (DFT) is implemented in order to reduce the failed parts to a very low level, guaranteeing the highest quality level needed in the market.

`Design-technology-co-hardening for voltage reference and linear voltage regulator based on bipolar technology

This article presents a radiation-hardened voltage reference and a radiation-hardened low-dropout (LDO) voltage regulator manufactured in bipolar technology for space environment applications. The output of voltage reference is adjustable in 2.5 V ∼ 30 V, with a supply voltage of 24 V. The LDO regulator operates from an input voltage range of 2.5–26 V and provides an output voltage of 1.5 V, with output voltage accuracy of ±0.5 %. The dropout voltage <700 mV at the full load current of 7A. It achieves line regulation and load regulation are <0.5 % over the entire operating temperature range. Through the circuit design of radiation hardening and the optimization of anti-radiation technology, both power management chips have single-event transient (SET) immunity at linear energy transfer (LET) of 37.4 MeV·cm2/mg. The output voltage deviation of rad-hard voltage reference is <0.6 % with total dose radiation tolerance of 100krad(Si) at 0.1 rad(Si)/s.

Accelerated ageing effects on the EMC performance of LDO regulators under multi-stresses: Experimental study and prediction approach

Low dropout voltage regulators (LDOs) play a crucial role in power management circuits. Unfortunately, long-term instability may threaten their functionality as well as their EMC performance, both concerning immunity and emission. The modeling of EMC deviations due to ageing degradation can assist to estimate the life expectancy of the LDOs and improve the reliability of the circuits. In this paper, a novel model is proposed to predict the conducted immunity deviations of LDOs based on convolutional neural networks and a long short-term memory (CNN LSTM) algorithm. It can explicitly learn the features of the conducted immunity in a wide frequency range and can accommodate multiple stresses which are applied to mimic the ageing process. The model is validated by carrying out an experiment where the DC (direct current) characteristics and conducted immunity performance are consistently monitored when the LDOs are subject to thermal-electrical-stresses in an ageing test. It can provide accurate immunity predictions and bypass the internal structure of the chips. It is shown that the proposed approach outperforms other models.

An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector

This article presents a synthesizable digital low-dropout regulator (DLDO) that precludes the use of an output load capacitor. For efficient regulation, the DLDO consists of fine and coarse loops that have different load conditions to operate. The dual loops are made of typical standard cells to improve the synthesizability. In the coarse loop, a comparator (CMP)-triggered oscillator is employed to generate a high-frequency clock signal without concerning the metastability in the CMP. In order to achieve a fast response to a voltage droop caused by load–current variation, a droop detector and latch-based drivers are exploited that are capable of compensating for a voltage droop asynchronously. The prototype of the DLDO was fabricated in 28-nm CMOS technology. A range of supply voltage is from 0.5 to 1.0 V with a 50-mV dropout voltage. Depending on a supply voltage, a maximum load current and a quiescent current are measured as 160-to-480 mA and 7.7-to-241 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> A, respectively. While a load current is increased from 20 to 450 mA with a 2-ns edge time, a 112-mV voltage droop and a 1.4-ns response time are achieved. Thanks to the synthesizability and the output-capacitor-free design, the DLDO occupies an 0.049-mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> total area and offers 9.8-A/mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> current density.

On‐chip bias‐generating architecture for an automotive application with a wide input dynamic range

SummaryThis paper presents an on‐chip bias‐generating architecture for automotive applications with a wide input range of 3.8–36 V in a 0.18‐ m high‐voltage bipolar‐CMOS‐DMOS (BCD) process. The proposed architecture effectively manages high‐voltage stress issues with few high‐voltage devices optimizing the silicon area. The proposed bias‐generator comprising crude‐reference and crude‐regulator generates a preliminary low bias voltage for the bandgap‐reference circuit. An adaptive‐biased, with‐capacitor, low‐dropout regulator generates a well‐regulated core supply with low quiescent current and better stability over the wide input range. The adaptive biasing expands the unity gain frequency with increasing load enabling a fast‐transient response. The proposed LDO provides a 5‐V output voltage and a load current of 10 A to 20 mA from 5.5‐ to 36‐V supply with a 500‐mV dropout voltage consuming a very low quiescent current of 5 A. With 0‐ to 20‐mA load step and an output capacitor of 1 F, an undershoot of 40 mV and an overshoot of 55 mV are achieved.

A 0.6 VIN 100 mV Dropout Capacitor-Less LDO with 220 nA IQ for Energy Harvesting System.

A fully integrated and high-efficiency low-dropout regulator (LDO) with 100 mV dropout voltage and nA-level quiescent current for energy harvesting has been proposed and simulated in the 180 nm CMOS process in this paper. A bulk modulation without an extra amplifier is proposed, which decreases the threshold voltage, lowering the dropout voltage and supply voltage to 100 mV and 0.6 V, respectively. To ensure stability and realize low current consumption, adaptive power transistors are proposed to enable system tropology to alter between 2-stage and 3-stage. In addition, an adaptive bias with bounds is utilized in an attempt to improve the transient response. Simulation results demonstrate that the quiescent current is as low as 220 nA and the current efficiency reaches 99.958% in the full load condition, load regulation is 0.0059 mV/mA, line regulation is 0.4879 mV/V, and the optimal PSR is -51 dB.

Design of Low-Drop-Out Voltage Regulator using CMOS Technology for Microprocessor Applications

The demand for electronic devices has increased due to continuous change in technology and its parameters. Low-Drop-Out [LDO] voltage regulator is utilised for power management and avoids unstable voltage in many electronicapplications.In this present investigation, a comprehensive characterization of a LDO in Complementary metal oxide semi-conductor technology [CMOS] is simulated using mentor graphics tool. The error amplifier of the low-drop-out voltage employed using 7 transistors for current mirroring technique. To manage the voltage differential, a pass transistor is created in a similar way utilising PMOS. Resistors and capacitors are passive components used in feedback network circuits and to reduce output voltage volatility, respectively. The suggested circuit achieves 140 mV of dropout voltage with a constant voltage of 1.6 V with a supply voltage range of 2 to 4.2 V and 4.16 mW of power consumption..

A Low-Power, Fast-Transient FVF-Based Output-Capacitorless LDO with Push–Pull Buffer and Adaptive Resistance Unit

An output-capacitorless low-dropout regulator (LDO) with a push–pull buffer was presented in this paper. The proposed push–pull buffer was able to provide a large charge and discharge current to increase the slew rate at the gate of the power transistor effectively, thereby improving the transient response of this LDO. In addition, an adaptive resistance unit (ARU) was proposed to solve the right half-plane zero problem caused by Miller compensation to optimize the loop stability of the LDO. The proposed LDO was implemented in a 0.18-µm CMOS technology. Simulation results showed that the quiescent current of this LDO was only 16.1 µA. It regulated the output at 1.5 V from a 1.8 V supply, with a dropout voltage of 300 mV at the maximum output current of 50 mA. The maximum value of the voltage spike was 129 mV. Additionally, the recovery time of the LDO was 0.2 µs.

Exploring Ways to Minimize Dropout Voltage for Energy-Efficient Low-Dropout Regulators: Viable approaches that preserve performance

Low-dropout (LDO) regulators are ideal off-chip and on-chip solutions for powering noise-sensitive loads, such as phase-locked loops, analog-to-digital converters, and sensor interfaces, because they convert voltage through a linear operation with no output voltage ripples. Wide bandwidth is one of the performance benefits of LDO regulators that lead to rapid transient response and superior power supply rejection (PSR). Furthermore, LDO regulators offer several advantages over switch-mode dc-dc converters, including a smaller die area and a more compact footprint (since they do not necessitate bulky passive components). Unfortunately, LDO regulators suffer from an inescapable disadvantage: poor power conversion efficiency (PCE); this is dominantly due to a considerable dropout voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DO</sub> ), which is the input-to-output differential voltage and applied across the pass transistor delivering output current. A small <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DO</sub> to improve efficiency, on the other hand, tends to drastically lower LDO regulators’ feedback loop gain, thereby causing a significant performance drop in aspects of PSR and voltage regulation performance. Because of this, most LDO regulators have been designed and developed with a large <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DO</sub> , leading many to view them as an inefficient part of the power management system. There is a wealth of tutorial literature that explains the fundamental principle of LDO regulators operating with a sufficient dropout voltage <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> , <xref ref-type="bibr" rid="ref2" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[2]</xref> , <xref ref-type="bibr" rid="ref3" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[3]</xref> , <xref ref-type="bibr" rid="ref4" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[4]</xref> , <xref ref-type="bibr" rid="ref5" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[5]</xref> , <xref ref-type="bibr" rid="ref6" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[6]</xref> , <xref ref-type="bibr" rid="ref7" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[7]</xref> , <xref ref-type="bibr" rid="ref8" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[8]</xref> . To the contrary, this article explores effective ways to extremely minimize the dropout voltage, without losing regulator performance, toward the realization of energy-efficient LDO regulators.