Drift Region Research Articles

Improvement the Breakdown Voltage and the On-resistance in the LDMOSFET: Double Buried Metal Layers Structure

In this paper, a new method is investigated to improve the breakdown voltage in the lateral power MOSFET transistors. The structure is based on Double Buried Metal Layers in the Lateral Diffused MOSFET and it is called DBML-LDMOSFET. The metal layers in the buried oxide under the drift region cause the electric field to be more uniform than the conventional structure. In the DBML-LDMOSFET Structure, the breakdown voltage is improved 25% compared to conventional structure and also the specific on-resistance is almost 11.32 mΩ.cm2. In order to investigate the performance of the structures, SILVACO-ATLAS software has been used and the results have been extracted.

Correlation between OCVD carrier lifetime vs temperature measurements and reverse recovery behavior of the body diode of SiC power MOSFETs

The reverse recovery (RR) behavior of SiC MOSFET body diode is of great importance in power application, where these devices are used in a wide range of operating temperatures. The carrier lifetime in the drift region varies with temperature, and it heavily affects the tailoring of the RR current, opening reliability issues related to the RR voltage amplitude and to possible anomalous voltage oscillations during the recovery. From the users' point of view, it would be useful to have a simple technique able to give predictive information about the body diode RR behavior of commercial devices over the whole range of working temperatures. An experimental-simulation approach is presented in this paper to correlate the carrier lifetime measured by simple OCVD measurements versus temperature with the RR behavior of the body diode, that can be useful at the design stage of power converters. Simulations of the body diode reverse-recovery are performed for a wide range of carrier lifetimes. This allows to estimate the effect of changes of carrier lifetime with temperature on the body diode switching transients. Preliminary results obtained with a 1700 V/5A commercial MOSFET are shown.

Enhanced Resolving Power by Moving Field Ion Mobility Spectrometry.

Ion mobility spectrometry is a powerful detection method widely used in various applications. Particularly in field applications, ion mobility spectrometers (IMSs) are useful because of their extremely low detection limits at short measuring periods and their compact and robust design. However, especially small IMSs suffer from the consequences of low resolving power when compared to laboratory systems. Therefore, in this paper, we present a new approach to increase the resolving power of a drift time IMS without employing higher drift voltages and bulky power supplies. The so-called moving field IMS (MOF-IMS) presented here allows a more effective use of the available voltage because of a segmented drift region where only a small part is supplied with voltage. Even with the basic version of an MOF-IMS presented here, it was possible to increase the resolving power by 60% from 60 to 95 without increasing the required drift voltage.

Field-Dependent Reduced Ion Mobilities of Positive and Negative Ions in Air and Nitrogen in High Kinetic Energy Ion Mobility Spectrometry (HiKE-IMS).

In High Kinetic Energy Ion Mobility Spectrometry (HiKE-IMS), ions are formed in a reaction region and separated in a drift region, which is similar to classical drift tube ion mobility spectrometers (IMS) operated at ambient pressure. However, in contrast to the latter, the HiKE-IMS is operated at a decreased background pressure of 10-40 mbar and achieves high reduced electric field strengths of up to 120 Td in both the reaction and the drift region. Thus, the HiKE-IMS allows insights into the chemical kinetics of ion-bound water cluster systems at effective ion temperatures exceeding 1000 K, although it is operated at the low absolute temperature of 45 °C. In this work, a HiKE-IMS with a high resolving power of RP = 140 is used to study the dependence of reduced ion mobilities on the drift gas humidity and the effective ion temperature for the positive reactant ions H3O+(H2O)n, O2+(H2O)n, NO+(H2O)n, NO2+(H2O)n, and NH4+(H2O)n, as well as the negative reactant ions O2-(H2O)n, O3-(H2O)n, CO3-(H2O)n, HCO3-(H2O)n, and NO2-(H2O)n. By varying the reduced electric field strength in the drift region, cluster transitions are observed in the ion mobility spectra. This is demonstrated for the cluster systems H3O+(H2O)n and NO+(H2O)n.

A Novel SiC MOSFET Embedding Low Barrier Diode With Enhanced Third Quadrant and Switching Performance

A novel planar gate SiC MOSFET embedding low barrier diode (LBD-MOSFET) with improved third quadrant and switching performance is proposed and characterized in this letter. The LBD-MOSFET not only exhibits about 3 times lower diode turn on voltage than the body diode, but also successfully eliminates bipolar degradation phenomena. A low potential barrier for electrons transporting from JFET region to N+ source region is formed in LBD-MOSFET owing to the existence of the depletion charge in LBD base region. Meanwhile, the gate-to-drain charge ( ${Q}_{\text {gd}}){}$ and gate-to-drain capacitance ( ${C}_{\text {gd}}){}$ of LBD-MOSFET are significantly reduced by about $21\times $ and $15\times $ in comparison with the conventional MOSFET (C-MOSFET), due to the reduction of the overlapping area of the gate and drift region. Therefore, the obtained high frequency figures of merit (HF-FOM $1= {R}_{\text {on,sp}}\times {Q}_{\text {gd}}$ and HF-FOM $2= {R}_{\text {on,sp}}\times {C}_{\text {gd}}$ ) for the LBD-MOSFET are improved by about 13 times and 9 times compared with C-MOSFET. Furthermore, a compact potential barrier analytical model based on Poisson’s Law is developed to understand the origin of low potential barrier diode in SiC LBD-MOSFET. The overall enhanced performances suggest SiC LBD-MOSFET is an excellent choice for high frequency power electronic applications.

Superjunction IGBT With Conductivity Modulation Actively Controlled by Two Separate Driving Signals

A dual-gate superjunction insulated gate bipolar transistor (IGBT) (DG-SJ-IGBT) is proposed and studied with numerical TCAD simulations. The new structure utilizes the superjunction structure as a controlling port for the strength of conductivity modulation inside the IGBT, so that a low ${V}_{\text {ON}}$ is obtained by a strong conductivity modulation during ON-state and a near-unipolar turn-off is achieved by removing the minority carriers before the turn-off event. For this purpose, the p-pillar in the DG-SJ-IGBT is connected to the p-body using a built-in p-channel MOSFET. The primary gate and the auxiliary gate (i.e., gate of p-MOSFET) are controlled by two separate driving signals. In the IGBT’s ON-state, the p-MOSFET disconnects the p-pillar, enabling full conductivity-modulated bipolar conduction and a consequent low ${V}_{\text {ON}}$ . As a well-known issue, conductivity modulation is accompanied by significant additional turn-off loss ( ${E}_{\text {OFF}}$ ). To overcome this issue, the DG-SJ-IGBT takes advantage of the p-pillar which extends through the entire drift region. Before the IGBT’s turn-off event, the p-MOSFET electrically grounds the p-pillar to the p-body. The grounded p-pillar serves as a hole extractor, suppresses the minority carrier density throughout the depth of the drift region, and brings the device into a near-unipolar conduction mode. Thus, a near-unipolar turn-off can be obtained, resulting in a low ${E}_{\text {OFF}}$ .

Improving the Current‐Spreading Effect for GaN‐Based Quasi‐Vertical PIN Diode by Using an Embedded PN Junction

GaN‐based quasi‐vertical PIN diodes are grown on insulating sapphire substrates, and thus both the n‐electrode and the p‐electrode are made on the same side, which causes lateral current injection scheme. Therefore, one of the challenges for this design lies in the serious current crowding at the mesa edges, which leads to the local hole accumulation, and thus the Auger recombination significantly gives rise to the poor conductivity modulation in the drift region when the devices are forwardly biased. Herein, utilizing an embedded PN–GaN junction is proposed, such that the embedded PN–GaN junction is reversely biased when the PIN diode is in the on‐state condition. The built‐in electric field in the reversely biased PN–GaN junction depletes holes at the mesa edges, and correspondingly the Auger recombination can be decreased. The results also show that the proposed structures do not affect the breakdown voltage for PIN diodes.

Reducing specific on-resistance for a trench SOI LDMOS with L-shaped P/N pillars

To reduce specific on-resistance (Ron,sp) of power devices, a novel SOI (silicon-on-insulator) trench gate LDMOS with heavily doping L-shaped P/N pillars and vertical dual-trench-gates is proposed in this paper, and its physical mechanism and electrical performance are investigated by numerical simulation. The L-shaped P-pillar raises the optimal doping impurity concentration of the drift region (Nd) remarkably from 1.7 × 1015 cm−3 to 1.25 × 1016 cm−3 by causing assistant depletion effect for drift region, hence a lower specific on-resistance (Ron,sp) with a 3.6 mΩ·cm2 is achieved. Meanwhile, the voltage capacity of the new structure is improved resulting from two new electric-field peaks produced by L-shaped P/N pillars. Consequently, a much lower Ron,sp and a higher breakdown voltage (BV) are achieved by the proposed structure. Simulated results show that the Ron,sp, BV, and Baliga’s figure of merit (FOM, FOM = BV2/Ron,sp) for the new structure are improved by 84.3%, 31.4%, and 991%, respectively, in comparison with the conventional trench LDMOS.

The IMOSFET: A Deeply-Scaled Fully-Self-Aligned Trench MOSFET

Silicon Carbide (SiC) power MOSFETs have made great progress since the first commercial devices were introduced in 2011, but they are still far from theoretical limits of performance. Above ~1200 V the specific on-resistance is limited by the drift region, but below 1200 V the resistance is dominated by the channel and the substrate, with smaller contributions from the source and the JFET regions. Trench MOSFETs generally have smaller cell area than planar DMOSFETs and are inherently more scalable. In this paper, we describe a highly self-aligned fabrication process to realize deeply-scaled trench MOSFETs with a cell pitch of 0.5 μm per channel. Since the narrow gate trench is shaped like a letter “I”, we refer to these devices as “IMOSFETs.”

Accelerated Testing of SiC Power Devices under High-Field Operating Conditions

Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation. During switching conditions, unexpected transient events may occur which force devices into avalanche or short circuit conditions. Moreover, silicon carbide devices typically experience higher fields in the gate oxide and drift regions than comparable Si devices due to channel and drift property differences. A summary of SiC MOSFET reliability and ruggedness test results are reported here. Reliability tests under high field conditions: positive-bias and negative-bias temperature instability (PBTI, NBTI) to examine threshold stability; time-dependent dielectric breakdown (TDDB) for gate oxide lifetime extrapolation; high-temperature reverse bias (HTRB); and HTRB testing under high neutron flux to determine terrestrial neutron single-event burnout (SEB) rates. High-power ruggedness evaluation is presented for SiC MOSFETs under forced avalanche conditions (unclamped inductive switching (UIS)) and under short-circuit operation to bound device safe operating areas. Overall results demonstrate the intrinsic reliability of SiC MOSFETs.

RESURF n-LDMOS Transistor for Advanced Integrated Circuits in 4H-SiC

The electrical behavior of lateral 4H-SiC n-laterally-diffused metal-oxide semiconductor (LDMOS) transistors with reduced surface field (RESURF) for integrated circuits was designed, measured, and modeled using different design variations. An additional implanted n-layer forming the drift region of the device in a p-doped epitaxy promotes a RESURF and thereby enhances the breakdown capability. The design rules of the presented power MOSFET are compatible to an existing technology for a novel 20-V 4H-SiC CMOS process. The dose of the additionally implanted RESURF region with a depth of approximately 390 nm was $3.5\cdot 10^{12}$ cm−2. Breakdown voltages in the range of 372–981 V and ON-state resistances from 1000 down to 54 $\text{m}\Omega $ cm2 were measured, depending on the design variations. The best measured figure-of-merit (FOM, ${V}_{{\mathrm {BD}}}^{2}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ) value results in 12.3 MW/cm2. Additionally, the electrical behavior of the presented n-LDMOS transistor was compared to a TCAD simulation model. Hereby, design guidelines concerning the length of the channel, drift region, and field plate were derived, which will be helpful for further investigations. Moreover, according to the simulations, a deeper RESURF region of $1~\mu \text{m}$ and a higher RESURF dose of $6\cdot 10^{12}$ cm−2 would even result in FOM values above 43 MW/cm2.

New high-voltage and high-speed β-Ga2O3 MESFET with amended electric field distribution by an insulator layer

The high wide-band-gap β-gallium oxide (β-Ga2O3) has attracted attention for high-voltage and high-speed applications over other wide-band-gap materials. In this work, we propose and demonstrate a β-Ga2O3 metal semiconductor field effect transistor (GO-MESFET) with an insulator layer (Si3N4) at the bottom of drift region (IL-GO-MESFET) to amend the potential and electric field distributions. In the proposed structure, we improve the electrical properties of the device such as unilateral power gain (U), maximum available gain (MAG), parasitic capacitance, noise figure, and breakdown voltage. The results show the IL-GO-MESFET structure has improved electrical properties and it has the great potential for using in high-voltage and high-speed applications.

An innovative TCAD simulated UHV-PLDMOS device with improved HTRB performance

This study proposed an innovative TCAD simulated ultra-high voltage p-type laterally diffused metal oxide semiconductor device structure with metal II field plate optimization (metal II is the second metal used on top of metal I with 10 000 Å Oxide dielectric in between as shown in figure ), which could improve high-temperature reverse-bias (HTRB) performance. By optimizing the metal II field plate position, the exposed area could be minimized, and furthermore, after using the passivation layer of oxide-(a-Si: H)-oxide-(a-Si: H)-nitride after stress, the hole trap concentration was much lower than that in the silicon nitride and silicon dioxide passivation region because of the low mobility of (a-Si: H), which was 1 cm2 v−1 s−1. The new passivation layer maintained the original p-drift reduced surface field (RESURF) doping profile and exhibited less degradation in terms of losing positive ions from the p RESURF channel crossing oxide and entering the traps. The five layers exhibited fewer traps; therefore, the degradation was improved. The reliability of the device could be increased by changing the doping concentration of the drift region according to the RESURF principle. In addition, this study compared two passivation layers of (oxide–silicon nitride) and five passivation layers of oxide- (a-Si: H)-oxide- (a-Si: H)-nitride.

A Generic Methodology for Breakdown Voltage Optimization of Lateral Silicon‐On‐Insulator Power Devices

A generic optimization methodology is presented for the design of drift region in lateral silicon‐on‐insulator (SOI) power devices. The methodology targets a drift region design with a low on resistance and a high reverse blocking capability. 2D drift diffusion technology computer aided design (TCAD) simulations are used to arrive at the principles of operation. As the drift region is a critical component of any lateral power device, the simulation domain is isolated to a generic n‐doped Si drift region, with symmetric top and bottom oxide () layers. A qualitative explanation based on charge sharing and the resulting electric field modulation is provided. The presence of oxide layers causes the drift region to be modulated such that it enables one to achieve a higher breakdown at a higher doping density. The main design parameters like drift doping, thickness, drift length, and oxide thickness are varied, and optimum values are identified for each. Finally, the extension of this optimization algorithm to other variants of lateral SOI devices is discussed.

New Power MOSFET with Beyond-1D-Limit RSP-BV Trade-Off and Superior Reverse Recovery Characteristics.

The application of conventional power metal-oxide-semiconductor field-effect transistor (MOSFET) is limited by the famous one-dimensional “silicon limit” (1D-limit) in the trade-off relationship between specific on-resistance (RSP) and breakdown voltage (BV). In this paper, a new power MOSFET architecture is proposed to achieve a beyond-1D-limit RSP-BV trade-off. Numerical TCAD (technology computer-aided design) simulations were carried out to comparatively study the proposed MOSFET, the conventional power MOSFET, and the superjunction MOSFET. All the devices were designed with the same breakdown voltage of ~550 V. The proposed MOSFET features a deep trench between neighboring p-bodies and multiple p-islands located at the sidewall and bottom of the trench. The proposed MOSFET allows a high doping concentration in the drift region, which significantly reduces its RSP compared to the conventional power MOSFET. The multiple p-islands split the electric field into multiple peaks and help the proposed MOSFET maintain a similar breakdown voltage to the conventional power MOSFET with the same drift region thickness. Another famous device technology, the superjunction MOSFET (SJ-MOSFET), also breaks the 1D-limit. However, the SJ-MOSFET suffers a snappy reverse recovery performance, which is a notorious drawback of SJ-MOSFET and limits the range of its application. On the contrary, the proposed MOSFET presents a superior reverse recovery performance and can be used in various power switching applications where hard commutation is required.

Reduction of unintentional Si doping in β-Ga2O3 grown via plasma-assisted molecular beam epitaxy

The authors investigate unintentional Si doping in β-Ga2O3 thin films grown via plasma-assisted molecular beam epitaxy. By identifying the Si dopant cell and the radio frequency oxygen plasma source as the two major sources of unintentional Si present in the growth chamber, adjustments to the parameters controlling these sources allow for the reduction of unintentional Si doping in β-Ga2O3 films by over two orders of magnitude. Decreasing the temperature of the Si dopant cell when idle reduces the unintentional doping from 2 × 1018 to 3 × 1017 cm−3. Furthermore, decreasing the oxygen plasma power from 300 to 250 and to 200 W results in the reduction of the unintentional Si doping from 3 × 1017 to 1 × 1016 cm−3. The reduction in unintentional Si doping concentration allows for low doping density in the drift region of β-Ga2O3 devices to design for high breakdown voltage via plasma-assisted molecular beam epitaxy.

A Trench-Field-Plate High-Voltage Power MOSFET

In this article, a trench-field-plate (TFP) high-voltage power MOSFET is proposed. Instead of using a conventional n− drift region, the TFP power MOSFET features benzocyclobutene dielectric in the sidewall of deep trenches in the drift region and a sloped field plate (FP) inside each of the trenches. The TFP structure employed in the drift region modulates the electric field in the OFF-state, resulting in a higher breakdown voltage (BV) than that of conventional power MOSFETs. Simulation results show that the specific ON-resistance of the TFP power MOSFET is approximately one-third that of the conventional power MOSFET and about 50% lower than that of the silicon limit for the same BV. In addition, compared with superjunction devices, the TFP power MOSFET is able to provide better reverse recovery characteristics, including a reduction in peak reverse recovery current ( ${I}_{{\text {RRM}}}{)}$ and reverse recovery charge ( ${Q}_{{\text {RR}}} {)}$ by 24% and 37%, respectively. Moreover, a p-i-n diode employing the TFP structure is fabricated, which is essentially identical to a power MOSFET in the OFF-state, to demonstrate the BV characteristics. The fabricated TFP p-i-n diode has a BV of 522 V, which is 2.3 times that of a conventional p-i-n diode fabricated on the same substrate.

Optimization and Comparison of Drift Region Specific ON-Resistance for Vertical Power Hk MOSFETs and SJ MOSFETs With Identical Aspect Ratio

This article proposes a MATLAB-based optimization methodology of the drift region specific ON-resistance ( ${R}_{on,sp}$ ) both for the high-permittivity ( $\text{H}{k}$ ) MOSFETs and superjunction (SJ) MOSFETs with design parameters expressed by breakdown voltage (BV) and aspect ratio (AR). The optimized method has three distinctive features. First, based on the built-in functions in MATLAB, the proposed method is very efficient to accurately obtain the optimized ${R}_{on,sp}$ ( ${R}_{on,sp(opt)}$ ) and the design parameters for both MOSFETs. Second, as the reflection of the process difficulty in the $\text{H}{k}$ or SJ structure, AR is used as one of the design variables. Third, the cubic polynomial functions are used to obtain a more accurate fitting for the optimization. The optimized results demonstrate that for a given BV, the ${R}_{on,sp(opt)}$ for the SJ MOSFET decreases as AR increases, whereas an optimum AR exists for a minimal ${R}_{on,sp(opt)}$ for the $\text{H}{k}$ MOSFET. Extensive comparisons demonstrate that when AR is small and BV is large, the ${R}_{on,sp(opt)}$ for the $\text{H}{k}$ MOSFET could be lower than that for the SJ MOSFET. Parameter designs are performed for the 900-V $\text{H}{k}$ MOSFET and SJ MOSFET. The impacts of important parameter variations on BV and ${R}_{on,sp}$ are also discussed. The validity of the proposed optimization method is demonstrated by the TCAD simulations.

Design Strategies for Mesa-Type GaN-Based Schottky Barrier Diodes for Obtaining High Breakdown Voltage and Low Leakage Current

In this article, we have systematically investigated the impact of different structural parameters on the breakdown voltage for GaN-based trench MIS barrier-controlled Schottky (TMBS) rectifier. Compared with the planar Schottky rectifier, the TMBS rectifier has field plates on the mesa sidewalls so that the drift region can be depleted in a 2-D manner, which helps to decrease the electric field at the metal/mesa interface. However, the adoption of mesas can make the electric potential lines at the mesa corner dense and has large curvatures. Therefore, the premature breakdown can occur when the electric field therein reaches the critical condition. We find that the electric field profiles can be affected by insulation layer thickness, mesa width, trench depth, and different types of insulation layers. Then, we increase the breakdown voltage by homogenizing the electric field distribution in the mesa region, e.g., the electric field at mesa corners can be decreased by adopting properly thick sidewall insulator and small trench depth. Meanwhile, TMBS rectifier using sidewall insulating material with a large dielectric constant more favors a large breakdown voltage.

Robust ESD-Reliability Design of 300-V Power N-Channel LDMOSs with the Elliptical Cylinder Super-Junctions in the Drain Side

The weak ESD-immunity problem has been deeply persecuted in ultra high-voltage (UHV) metal-oxide-semiconductor field-effect transistors (MOSFETs) and urgently needs to be solved. In this paper, a UHV 300 V circular n-channel (n) lateral diffused MOSFET (nLDMOS) is taken as the benchmarked reference device for the electrostatic discharge (ESD) capability improvement. However, a super-junction (SJ) structure in the drain region will cause extra depletion zones in the long drain region and reduce the peak value of the channel electric field. Therefore, it may directly increase the resistance of the device to ESD. Then, in this reformation project for UHV nLDMOSs to ESD, two strengthening methods were used. Firstly, the SJ area ratio changed by the symmetric eight-zone elliptical-cylinder length (X) variance (i.e., X = 5, 10, 15 and 20 μm) is added into the drift region of drain side to explore the influence on ESD reliability. From the experimental results, it could be found that the breakdown voltages (VBK) were changed slightly after adding this SJ structure. The VBK values are filled between 391 and 393.5 V. Initially, the original reference sample is 393 V; the VBK changing does not exceed 0.51%, which means that these components can be regarded as little changing in the conduction characteristic after adding these SJ structures under the normal operating conditions. In addition, in the ESD transient high-voltage bombardment situation, the human-body model (HBM) capability of the original reference device is 2500 V. Additionally, as SJs with the length X high-voltage P-type well (HVPW) are inserted into the drain-side drift region, the HBM robustness of these UHV nLDMOSs increases with the length X of the HVPW. When the length X (HVPW) is 20 μm, the HBM value can be upgraded to a maximum value of 5500 V, the ESD capability is increased by 120%. A linear relationship between the HBM immunity level and area ratio of SJs in the drains side in this work can be extracted. The second part revealed that, in the symmetric four-zone elliptical cylinder SJ modulation, the HBM robustness is generally promoted with the increase of HVPW SJ numbers (the highest HBM value (4500 V) of the M5 device improved by 80% as compared with the reference device under test (DUT)). Therefore, from this work, we can conclude that the addition of symmetric elliptical-cylinder SJ structures into the drain-side drift region of a UHV nLDMOS is a good strategy for improving the ESD immunity.