Drain Side Research Articles

Performance Analysis of Gate-Stack Dual-Material DG MOSFET Using Work-Function Modulation Technique for Lower Technology Nodes

Short channel effects (SCEs) along with mobility degradation has a great impact on CMOS technology below 100 nm. These effects can be overcome by using gate and channel engineering techniques which will improve mobility of the charge carriers, thus eventually improving drain current and trans-conductance of the device. In this work, the speed of operation for DG MOSFET is improved by reducing the channel length where dual-material gate-stack is deployed to avoid the drain-induced barrier lowering (DIBL) and hot carrier effects. In the presented device, the metal closer to the source and drain has higher and lower work function, respectively which causes a significant decrement in the peak electric field at the drain side and so the SCEs. The carrier mobility is also increased due to enhanced electric field in the channel, near the source, caused by higher work function gate material which, in turn, increases the MOSFET’s driving current. The screening effect reducing SCEs and an increment in the acceleration of the charge carriers in the channel are mainly attributed due to higher and lower threshold voltage found near the source and drain, respectively.

Improvement of a Novel SOI- MESFET with an Embedded GaN Layer for High-Frequency Operations

In this paper, we propose a novel Silicon on Insulator (SOI) Metal Semiconductor Field Effect Transistor (MESFET) with an embedded GaN layer (GL-SOI-MESFET) for modifying the electric field distribution. The main idea of this work is based on using a high breakdown field material (GaN), for amending the electric field and potential distribution near the drain region, and as a result, the breakdown voltage of the proposed structure will be higher than a conventional structure (C-SOI-MESFET). The breakdown voltage (VBR) of the GL-SOI-MESFET at the Ids = 55 mA/mm and Vgs = − 1 V has been achieved ~21 V whereas the VBR in the C-SOI-MESFET is 16 V. The proposed structure shows the improvement of DC and RF characteristics versus the C-SOI-MESFET. For obtaining the best results to improve the structure performance, dimensions of the GaN layer have been optimized. Also, by amending potential distribution and changing the depletion region between the gate and drain sides, the gate-drain capacitance reduces. The effects like the electric field, the potential distribution, breakdown voltage, the kink effect, the self-heating effect, power gains, and parasitic capacitances are investigated and the proposed structure results have superior DC and radio frequency (RF) performances compared with the conventional MESFET structure.

Analysis of Threshold Voltage Shift for Full VGS/VDS/Oxygen-Content Span under Positive Bias Stress in Bottom-Gate Amorphous InGaZnO Thin-Film Transistors.

In this study, we analyzed the threshold voltage shift characteristics of bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) under a wide range of positive stress voltages. We investigated four mechanisms: electron trapping at the gate insulator layer by a vertical electric field, electron trapping at the drain-side GI layer by hot-carrier injection, hole trapping at the source-side etch-stop layer by impact ionization, and donor-like state creation in the drain-side IGZO layer by a lateral electric field. To accurately analyze each mechanism, the local threshold voltages of the source and drain sides were measured by forward and reverse read-out. By using contour maps of the threshold voltage shift, we investigated which mechanism was dominant in various gate and drain stress voltage pairs. In addition, we investigated the effect of the oxygen content of the IGZO layer on the positive stress-induced threshold voltage shift. For oxygen-rich devices and oxygen-poor devices, the threshold voltage shift as well as the change in the density of states were analyzed.

Performance Enhancement of GAA Multi-Gate Nanowire with Asymmetric Hetero-Dielectric Oxide

In this paper, a Multi-gate asymmetric hetero-dielectric oxide gate all around nanowire MOSFET device (MG-AHD–GAA-NW) is proposed for the low power standby, memory and sensor applications. The architecture of the proposed device is supported by segmented multiple gate with asymmetric hetero-dielectric oxide high-K(HfO2/TiO2) on the source side and SiO2 on drain side. Firstly, the effect of silicon thickness on conventional single gate cylindrical GAA MOSFET is studied. On reducing the thickness of silicon, a decrease in OFF current is observed. Further, to achieve best performance of the device at reduced silicon thickness(tSi = 5 nm) with quantum confinement effects, the proposed device is introduced. It is observed that at reduced silicon thickness (tSi = 5 nm), a low leakage current of 10−14A and ON current of 10−5A is obtained. The comparison of MG-AHD–GAA-NW with conventional single gate cylindrical GAA at tSi = 5 nm shows decrease in OFF current and increase in ON/OFF current ratio by 67.4% and 230% in MG-AHD–GAA-NW at same silicon thickness respectively. The proposed model is analysed by the various performance metrics such as transconductance(gm), and device efficiency(gm/ID).The proposed device exhibits lower DIBL of 16.7 mV/V, improved subthreshold slope of 62.28 mV/decade, higher ON/OFF current ratio of 8.87 × 108, higher transconductance and optimal threshold voltage. The effect of traps in semiconductor/gate oxide interface on device performance is also studied. Finally, to achieve the best performance of the device at circuit level implementation, the results of PMOS are matched with NMOS using work function engineering and thus V-shaped curve is obtained for both type of MOSFET followed by CMOS inverter as an application is also presented using the proposed device structure.

Transient Measurement of GaN HEMT Drift Region Potential in the High Power State

This work reports the transient measurement of the AlGaN/GaN high electron-mobility transistor (HEMT) drift region potential in the high power state during switching. The effect of high power stress has been reported by device characterization after stress or during high power DC stress at voltages below the operating voltages to avoid device failure. However, transient measurement during high power stress is challenging, since the device can sustain the high power stress only for a few μs before failure occurs. In this work, a test structure with voltage probe inserted in the drift region between the gate and the drain is used to perform real-time measurement of the drift region potential during the high power state at operating voltages. It is found that the high electric field formed at the gate side during the off-state stress propagates towards the drain side within a few μs. The propagation speed of this high electric field increased with increase in drain voltage. It is proposed that trapping of hot channel electrons is causing this effect, and dynamic on-resistance measurement suggests that the traps are 0.44 eV below the conduction band.

Raised Source/Drain (RSD) and Vertical Lightly Doped Drain (LDD) Poly-Si Thin-Film Transistor

The raised source/drain (RSD) structure is one of thin film transistor designs that is often used to improve device characteristics. Many studies have mentioned that the high impact ionization rate occurring at a drain side can be reduced, owing to a raised source/drain area that can disperse the drain electric field. In this study, we will discuss how the electric field at the drain side of an RSD device is reduced by a vertical lightly doped drain (LDD) scheme rather than a RSD structure. We used different raised source/drain forms to simulate the drain side electric field for each device, as well as their output characteristics, using Integrated Systems Engineering (ISE-TCAD) simulators. Different source and drain thicknesses and doping profiles were applied to verify the RSD mechanism. We found that the electric fields of a traditional device and uniform doping RSD structures are almost the same (~2.9 × 105 V/cm). The maximum drain electric field could be reduced to ~2 × 105 V/cm if a vertical lightly doped drain RSD scheme was adopted. A pure raised source/drain structure did not benefit the device characteristics if a vertical lightly doped drain design was not included in the raised source/drain areas.

A Dielectrically Modulated GaN/AlN/AlGaN MOSHEMT with a Nanogap Embedded Cavity for Biosensing Applications

In this work, GaN/AlN/AlGaN MOS-HEMT with a cavity below the gate towards the drain side is studied for its sensitivity analysis and viability as a biosensor. The analysis is done by dielectric modulation of the cavity region to emulate the presence of different dielectric biomolecules and charged biomolecules by interface charge variation. MOSFET-based dielectrically modulated sensors have been a success experimentally and this work extends and demonstrates this concept with GaN HEMT. The device performance is evaluated through the shift in threshold voltage (V th) and drain current (I DS), which are used as performance metrics. The proposed device structure simulations were performed with ATLAS Silvaco device simulation tool which depicts the bio-immobilization in the cavity leads to the changes in electrostatic properties like conduction band offset, two-dimensional electron gas (2DEG) sheet carrier concentration and channel potential. The simulation analysis reveals V th and I DS shift up to 1.1 V and 153.7 mA/mm for the neutral biomolecules, whereas for deoxyribo nucleic acid, the shift is up to 0.30 mV and 65.2 mA/mm, respectively, implying a highly sensitive device. The AlGaN layer thickness and cavity fill height variations on device sensitivity are also reported.

Design and Analysis of Gate Overlapped/Underlapped NWFET Based Lable Free Biosensor

In this paper, gate all around (GAA) nanowire P-channel FET label free biosensor is proposed with cavity. Proposed structure is label free so it doesn’t require selective material for specific biomolecule enzymes. High surface to volume ratio provide good sensitivity which is crucial for any biosensor application. To sense the kind of biomolecule, there is a cavity created at the gate, so biological elements like enzymes interact with cavity and it changes the carrier concentration which in turn changes the current. In addition to this, first biosensor structure is analyzed with cavity at the source side and second structure is analyzed with cavity at the drain side. Length of cavity is varied from 10 nm to 40 nm for optimization of the proposed biosensor structure. This biosensor is used to find the amount of biomolecule present in aqueous solution through their enzymes. To estimate the sensing capability of this sensor, testing is done using glucose molecules. We observed comparatively better sensitivity when cavity is placed at drain side.

Research on ESD Protection of Ultra-High Voltage nLDMOS Devices by Super-Junction Engineering in the Drain-Side Drift Region

Electrostatic discharge (ESD) transient events can often damage semiconductor components. Therefore, the ultrahigh-voltage (UHV) circular n-channel lateral diffused metal-oxide-semiconductor transistor (nLDMOS) usually used in power electronics needs to have ESD self-protection capabilities. In this paper, the geometric parameters of 300-V and 200-V UHV circular nLDMOSs were modulated using different layouts at the drain side. The high-voltage p-well (HVPW) layer was used to form various super junctions (SJs) in the drift region. The modulations were classified as SJ length, SJ concentration-gradient thickness, HVPW ring-sector, and rotated SJ concentration gradient modulations in the drift region. Various HVPWs were used to produce several SJs in the drain drift region. According to the final measurement results, all modulation processes maintained the original physical characteristics of high breakdown voltage. Devices with the SJ length and SJ concentration-gradient thickness’s modulations provided the best ESD robustness. The ESD testing value of the human-body model (HBM) will increase with the increase of the SJ length and SJ thickness modulations. The HBM value increased from the 1500 V reference to 4000V (increased by 166.66%).

Electromigration in Power Devices: A Combined Effect of Electromigration and Thermal Migration

Abstract In the power semiconductor industry, there is continuous development toward higher maximum current capability of devices while device dimensions shrink. This leads to an increase in current density which the devices have to handle, and raises the question if electromigration (EM) is a critical issue here. Generally, an EM failure can be described by the Black’s equation with temperature and current density as the main influencing factors. Normally, the current that the power packages need to handle lies in the range of 100 A. However, it should be noted that power devices exhibit asymmetric sizes of drain and source contacts. This may lead to higher current density at the source leads (area ratio drain/source: ~9× for PQFN 5 × 6). Nevertheless, the source lead area is still much larger than that of the flip chip bumps (i.e., 28 times larger than a 100-μm microbump). This typically enhances the safety of the power device with respect to EM. However, with regard to future development toward higher maximum current capability, we intended to investigate further on the EM of power devices. In the present work, we focused on the PQFN 5 × 6 package to study the EM behavior of a power device soldered on a printed circuit board (PCB). We employed the highest current (120 A) and temperature (150°C) that the stress test system could handle to study EM in accelerated mode. First fails occurred after ~1,200 h, which was much earlier than expected from previous flip-chip investigations. In addition, we found separation gaps in the solder joint between drain contact and PCB, which experienced the lowest current density in the whole test. Contradictorily, we observed only minor solder degradation at the source interface, regardless of the higher current density there. Nevertheless, the separating metal interfaces still correlated well with the current direction. Thermal simulations revealed that due to the self-heating of the device by the high current applied, both the drain and source leads were exposed to much higher temperatures (Tmax = 168°C) than the PCB board which was kept under temperature control at 150°C. This temperature difference resulted in a thermal gradient between the device and PCB, which, in turn, triggered thermal migration (TM) in addition to EM. As TM for the drain contact occurred in the same direction as EM, it enhanced the degradation effect and therefore led to a shorter time-to-failure at the drain. In contrast to this, such an enhanced effect did not occur at the source side. As a result, we observed higher solder degradation at the drain side, which we did confirm by switching the current direction in the test. To minimize the TM effect, a special EM test vehicle, which used a Cu plate instead of the metal-oxide-semiconductor field-effect transistor chip, was designed and fabricated. Thermal simulation verified that the device operated at similar temperatures as the PCB board. Using this setup, it was possible to study EM in an accelerated mode and, thus, investigate the pure EM behavior of the power device.

Sensitivity Analysis on Dielectric Modulated Ge-Source DMDG TFET Based Label-Free Biosensor

This work compares the performance of dielectric modulated (DM) based Ge-source dual material double gate (DMDG) Tunnel Field Effect Transistor (TFET) and conventional (C)-DMDG-TFET as label free biosensor through Technology Computer Aided Design (TCAD) simulator. Here, cavity is introduced both at source and drain sides of the fixed HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric to increase the capture area of biosensors. Sensitivity (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> ) is extracted for both neutral and charged (positive/negative) biomolecules considering cavity is fully filled with different dielectric materials (k). We have reported the sensitivity with the variation in height of nanogap cavity (h <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bio</sub> ) for neutral biomolecules in the cavity. The sensitivity of Ge-source DMDG-TFET is found higher than C-DMDG-TFET due to more conduction at the tunnel junction. Also, the subthreshold swing (SS), transfer characteristics, and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio of these biosensors are reported for different k and h <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bio</sub> considering neutral/charged biomolecules. The sensitivity of partially filled nanogaps with biomolecules like decreasing, increasing, concave, and convex step profiles are reported for both the biosensors. The dynamic range (DR) of both the biosensors are extracted in presence of positive and negative charged biomolecules. The response time of Ge-source DMDG-TFET is reported at different k. A comparative study of proposed biosensor with other reported work is discussed. Finally, the sensitivity is extracted for DMDG-TFET considering other source material like GaAs, InAs, Si-Ge hetero stacked (HS), GaAs-InAs HS.

Enhance the ESD Ability of UHV 300-V Circular LDMOS Components by Embedded SCRs and the Robustness P-Body Well

The ultra-high voltage (UHV) Lateral-diffused MOSFET (LDMOS) transistor has been widely used in power circuit applications and also used as an electrostatic discharge (ESD) self-protection device. However, the ESD ability of an UHV LDMOS is generally worse than that of low- and high-voltage (HV) devices, which means this UHV LDMOS device can be easily failed under an ESD event. Then, the method of embedded a silicon-controlled rectifier (SCR) into the HV LDMOS has been used in the HV circuit as an ESD protection technique. But when this architecture is applied to UHV devices, will its ESD capability be as good as in HV devices? A novel SCR with a P-body well architecture is proposed, which can effectively enhance the ESD ability of the UHV nLDMOS device when the drain side is embedded this new structure. The proposed structure can greatly improve the ESD capability of the device without adding any extra process step (& photomask), layout area and affecting the basic breakdown voltage. Finally, the proposed structure of the PPP-arranged type with the P-body well can greatly increase the ESD (FOM) ability which $\text{I}_{\mathrm{ t2}}$ and HBM ability can be increased by 68.7% and 22.2% (72.9%), respectively, as compared with the conventional SCR PPP-arranged type.

Gated two-dimensional electron gas in magnetic field: Nonlinear versus linear regime

We study the effect of magnetic field on the properties of a high mobility gated two-dimensional electron gas in a field effect transistor with the Hall bar geometry. When approaching the current saturation when the drain side of the channel becomes strongly depleted, we see a number of unusual effects related to the magnetic field induced re-distribution of the electron density in the conducting channel. The experimental results obtained in the non-linear regime have been interpreted based on the results obtained in the linear regime by a simple theoretical model, which describes quite well our observations.

Pseudo Split Gate In0.53Ga0.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis

AbstractIn this work, we present the design and simulation of a novel structure of In0.53Ga0.43As/InP based hetero junction tunnel field effect transistor (HTFET). The proposed HTFET employs two gates: the conventional main gate and a pseudo split gate (PSG) at the drain side. The PSG is placed at the top of the drain region with the same equivalent oxide thickness (EOT) and work function as that of the main gate at an optimized separation from gate electrode. The PSG is not an active gate and it is not connected to either VDD or gate voltage. Two dimensional simulation study has revealed that the proposed device suppresses ambipolar current by ~10 orders of magnitude as compared to a HTFET without overlap and by &gt;7 orders as compared to overlapping gate on drain HTFET (OGD‐HTFET). The PSG‐based HTFET (PSG‐HTFET) also exhibits lesser total gate capacitance as compared to OGD TFET. The proposed PSG‐HTFET offers much better ambipolar suppression even at higher drain doping and lower EOT, as compared to OGD‐HTFET. Further, the PSG‐HTFET exhibits 50% and 40% lesser fall and rise propagation delays respectively as compared to the OGD‐HTEFT. Further, the voltage overshoot and undershoot have also been suppressed in the proposed PSG‐HTFET. The scalability analysis shows that the PSG‐HTFET has better scalability in terms of ambipolar suppression, total gate capacitance, and propagation delays.

Improved reverse recovery characteristics obtained in 4H‐SiC double‐trench superjunction MOSFET with an integrated p‐type Schottky diode

A novel double-trench superjunction SiC metal–oxide–semiconductor field-effect transistor (MOSFET) with an integrated Schottky contact at the drain side is proposed in this study. Results indicate an improvement of 58% in reverse recovery current I rrm /charge Q rr and 22% in the trench corner electric field E ox − m compared to the device without Schottky and without superjunction, respectively. This comparison became possible using mixed mode simulations in Sentaurus TCAD. While the improvement in electric field is due to incorporation of superjunction concept along the drift region, the improvement of reverse recovery is due to Schottky contact forming a barrier for the charge carriers. Using calibrated two-dimensional numerical simulations, the authors were able to demonstrate the influence of Schottky contact on reverse recovery current of the device. The superiority of the proposed device is presented by plotting the switching energy loss with respect to external gate resistance and temperature through non-isothermal simulations.

Dynamics of surface electron trapping of a GaN-based transistors revealed by spatiotemporally resolved x-ray spectroscopy

Gallium nitride (GaN)-based transistors are promising for realizing ultralow latency of wireless information communications that are indispensable for smart societies. However, surface states have slow time constants of (de)trapping electrons and delay electrical signal responses of the transistors, which prevent the ultralow latency. To clarify the mechanism of surface electron trapping (SET) of GaN-based transistors, which varies spatiotemporally, we studied the dynamics of the SET by using spatiotemporally resolved x-ray spectroscopy. We directly observed that neutralization of donor-like surface states occurs only near the gate edge in the drain side just after switching off the bias. We found that the large local electric field formed by the bias application induces site- and time-specificity in the SET, which leads to the delayed responses. Our proposed mechanism will be useful for optimizing the transistor structure to achieve the ultralow latency.

Drain-engineered vertically stacked junctionless FET exhibiting complementary operation

In this work, a multifunctional drain-engineered (DE) vertically stacked (VS) junctionless (JL) FET exhibiting device reconfigurability and its application as an inverter are proposed and simulated. The proposed DE VS JL FET consists of stacked $${n}^{+}$$ and $${p}^{+}$$ device layers having SiO $$_{2}$$ isolation vertically, with n-drain ( $${D}_n$$ ) and p-drain ( $${D}_p$$ ) silicide regions connected together. Highly doped device layers allow for the formation of a thin-dopant segregation layer on the drain side. To mimic the realistic channel/drain junctions, silicides with realistic Schottky-barrier heights are chosen ( $${D}_n$$ : $$\hbox {ErSi}_x$$ $$\approx $$ 0.28 eV and $${D}_p$$ : PtSi $$\approx $$ 0.24 eV). Both device layers contribute individually to the n-FET and p-FET complementary operation when biased adequately. Moreover, the transient analysis shows that the device in the inverter mode performs reasonably well even when the $${V}_{\text {DD}}$$ is scaled up to 0.5 V. Furthermore, a 3-transistor-based 2-input XOR gate standard cell has also been realized using the proposed device.

Simulation Study of Dielectric Modulated Dual Material Gate TFET Based Biosensor by Considering Ambipolar Conduction

In this paper, a dielectric modulated dual material gate TFET (DM-DMG_TFET)based biosensor is proposed. In order to detect various biomolecules, a nanogap cavity is formed by the overlapping the gate on the drain side. The change in ambipolar current is considered as the sensing parameter by changing the dielectric constants of various immobilized biomolecule inside the nano cavity. A complete investigation on the performance of the biosensor is also done by considering different positions and filling factor of the biomolecules inside the nano cavity region. The dual-material gate structure is considered with dissimilar work functions (фM1 < фM2), which can effectively reduce the ambipolar current by enhancing the barrier width at channel-Drain junction. The proposed structure deliberately reduces ambipolar current and increases the sensitivity as compared to the single material gate structure. In this work we report a drift in the sensitivity from 104 to 106 for low dielectric constant biomolecules.

Performance Tuning and Reliability Analysis of the Electrostatically Configured Nanotube Tunnel FET with Impact of Interface Trap Charges

This paper examines, an electrostatically configured Nano-Tube Tunnel Field-Effect Transistor (ED-NTTFET). During the fabrication process, different charges such as fixed charge, oxide trapped charge, and interface trapped charge have been produced at the gate oxide interface. So the effect of positive and negative interface trapped charge (+ITC & -ITC) has been proposed for the first time for electrostatic doped-based Nano-Tube TFET (ED-NTTFET). There are two types of techniques, charge plasma (EP) based technique and electrostatic doped (ED) technique is used to produce the induced charge in the intrinsic channel region. In the charged plasma (CP) technique, the metal work-function is used to produce the induced charge while in the electrostatic doped (ED) technique electrostatic voltage is applied across the source and drain side to produce the induced charge in the intrinsic channel region. Analysis of the various device parameters such as hole/electron concentration, energy diagram, electric field, tunneling rate, driving current, OFF current, ON current, ION/IOFF, threshold voltage, and average sub-threshold slope in the presence of interface trapped charge (ITC). Due to positive interface trapped charge electric field and band to band tunneling rates are improved. So the drain current of the device also improved from the 2.94*10−5 A/um2 to 5.35*10−5A/um2. Linearity parameters such as second & third order trans-conductance (gm2 & gm3), second & third order voltage intercept point (VIP2 & VIP3), second & third order harmonics distortions (HD2 & HD3) and intermodulation distortions (IMD) have been discussed. The negative interface trapped charge (-ITC) degrades the linearity parameter of the device and the positive interface trapped charge (+ITC) improves the linearity parameter of the device. The proposed electrostatic doped nano-tube TFET (ED-NTTFET) produced higher cut-off frequency at lowers operating gate voltage.

Improvement in electrostatic effeciency using workfunction modulated dual metal gate FinFET

This paper demonstrates a 3-D simulation study of a workfunction modulated dual material gate FinFET (WMDMGF). The source side gate material workfunction of a dual material gate FinFET is modulated linearly keeping drain side material workfunction to be constant. This model provides improvement in terms of DC performance such as better drive current and minimum threshold voltage. Thus, enhancing the switching characteristics of the device and providing better speed. The model is simulated using Silvaco TCAD tool, and the results are compared with single metal gate and dual metal gate FinFET performance.