Performance Enhancement of GAA Multi-Gate Nanowire with Asymmetric Hetero-Dielectric Oxide

Abstract

In this paper, a Multi-gate asymmetric hetero-dielectric oxide gate all around nanowire MOSFET device (MG-AHD–GAA-NW) is proposed for the low power standby, memory and sensor applications. The architecture of the proposed device is supported by segmented multiple gate with asymmetric hetero-dielectric oxide high-K(HfO2/TiO2) on the source side and SiO2 on drain side. Firstly, the effect of silicon thickness on conventional single gate cylindrical GAA MOSFET is studied. On reducing the thickness of silicon, a decrease in OFF current is observed. Further, to achieve best performance of the device at reduced silicon thickness(tSi = 5 nm) with quantum confinement effects, the proposed device is introduced. It is observed that at reduced silicon thickness (tSi = 5 nm), a low leakage current of 10−14A and ON current of 10−5A is obtained. The comparison of MG-AHD–GAA-NW with conventional single gate cylindrical GAA at tSi = 5 nm shows decrease in OFF current and increase in ON/OFF current ratio by 67.4% and 230% in MG-AHD–GAA-NW at same silicon thickness respectively. The proposed model is analysed by the various performance metrics such as transconductance(gm), and device efficiency(gm/ID).The proposed device exhibits lower DIBL of 16.7 mV/V, improved subthreshold slope of 62.28 mV/decade, higher ON/OFF current ratio of 8.87 × 108, higher transconductance and optimal threshold voltage. The effect of traps in semiconductor/gate oxide interface on device performance is also studied. Finally, to achieve the best performance of the device at circuit level implementation, the results of PMOS are matched with NMOS using work function engineering and thus V-shaped curve is obtained for both type of MOSFET followed by CMOS inverter as an application is also presented using the proposed device structure.