Drain Junction Capacitance Research Articles

Determination of the Drain Saturation Voltage of a Metal–Oxide–Semiconductor Field-Effect Transistor by the Capacitance–Voltage Method

In this paper, we present a simple technique to extract drain saturation voltage using the drain junction capacitance–voltage data of a metal–oxide–semiconductor field-effect transistor (MOSFET). When voltage is applied to the gate terminal, the drain and source are connected electrically via a surface inversion charge, and drain junction capacitance increases. When drain voltage increases, the pinch-off occurs at the drain end of the channel, and drain junction capacitance is rapidly reduced. Through this phenomenon, we can extract the drain saturation voltage directly from the drain junction capacitance–voltage curve without using complex mathematical formulas.

Impact of Lateral Asymmetric Channel Doping on 45-nm-Technology N-Type SOI MOSFETs

Lateral asymmetric channel doping is applied to 45-nm technology NFET devices. The measured effective drain-current enhancement over coprocessed symmetric control devices is 10%. Analysis reveals that the dominant physical mechanism, which accounts for two-third of the total enhanced drain current, is an 8% increase in the source-side injection velocity. The remaining one-third is attributed to the decreased drain-induced barrier lowering. This paper concludes with an analysis of the switching characteristics of CMOS inverters composed of an asymmetric NFET and a companion symmetric PFET and shows a 5% improvement in the delay. The improvement is explained in terms of the increased velocity and 30% reduction in drain junction capacitance.

Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits

Partially depleted silicon-on-insulator (PD-SOI) technology has garnered more attention recently with regards to replacing traditional bulk-silicon technology as the mainstream technology of choice for high-performance/low-power digital applications. The increase in performance is due to the buried oxide layer, which provides a dramatic decrease in the source and drain junction capacitance, as well as a reduction in the traditional back biasing resulting from the body effect. The reported performance increases have been between 20% and 35%. However, this increase in performance comes at a cost of complexity from a performance measurement and delay testing perspective. Where the SOI transistor is faster than the bulk transistor, there exists a variation in delay caused by threshold voltage shifts that must be accounted for during manufacturing test. This paper explores these issues and proposes new test techniques for this promising technology

Highly Linear 0.18-<tex>$mu$</tex>m CMOS Power Amplifier With Deep n-Well Structure

The linearity of a 0.18-/spl mu/m CMOS power amplifier (PA) is improved by adopting a deep n-well (DNW). To find the reason for the improvement, bias dependent nonlinear parameters of the test devices are extracted from a small-signal model and a Volterra series analysis for an optimized nMOS PA with a proper matching circuit is carried out. From the analysis, it is revealed that the DNW of the nMOS lowers the harmonic distortion generated from the intrinsic gate-source capacitance (C/sub gs/), which is the dominant nonlinear source, and partially from drain junction capacitance (C/sub jd/). Single-ended and differential PAs for 2.45-GHz WLAN are designed and fabricated using a 0.18-/spl mu/m standard CMOS process. The single-ended PA with the DNW improves IMD3 and IMD5 about 5 dB with identical power performances, i.e., 20 dBm of P/sub out/, 18.7 dB of power gain and 31% of power-added efficiency (PAE) at P/sub 1dB/. The IMD3 and IMD5 are below -40 dBc and -47dBc, respectively. The differential PA with the DNW also shows about 7 dB improvements of IMD3 and IMD5 with 20.2 dBm of P/sub out/, 18.9 dB of power gain and 35% of PAE at P/sub 1dB/. The IMD3 and IMD5 are below -45 dB and -57 dBc, respectively. These performances of the linear PAs are state-of-the-art results.

Design of a 0.1 µm single halo (SH) thin film silicon-on-insulator (SOI) MOSFET for analogue applications

In this paper, we propose a design of a 0.1 µm single halo (SH) thin film silicon-on-insulator (SOI) nMOSFET device for analogue and mixed signal applications. The single halo structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. The design methodology is based upon the improvement in the short-channel effects (SCE) and suppression of the kink. The device is optimized for various film thicknesses and different peak dopings. The position of the peak doping near the source is also an important parameter and hence, also needs to be optimized. The SH devices show better Vth–L roll-off, low drain induced barrier lowering, higher breakdown voltages and lower floating-body effects. The experimental results have shown the superior analogue performance of SH SOI MOSFETs. Also, the low drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance.

Asymmetric Halo CMOSFET to Reduce Static Power Dissipation With Improved Performance

In this paper, we show the benefits of using asymmetric halo (AH, different source, and drainside halo doping concentrations) MOSFETs over conventional symmetric halo (SH) MOSFETs to reduce static leakage in sub-50-nm CMOS circuits. Device doping profiles have been optimized to achieve minimum leakage at iso on-current. Results show a 61% reduction in static leakage in AH nMOS transistor and a 90% reduction in static leakage in AH pMOS transistor because of reduced band-to-band tunneling current in the reverse biased drain-substrate junctions. In an AH CMOS inverter, static power dissipation is 19% less than in an SH CMOS inverter. Propagation delay in a three-stage ring oscillator reduces by 11% because of reduced drainside halo doping and hence reduced drain junction capacitance. Further comparisons have been made on two-input NAND and NOR CMOS logic gates.

Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications

In this paper, for the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for analog and mixed-signal applications. The SH structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Besides excellent dc output characteristics and experimental characterization results on these devices show better V/sub th/-L roll-off, low DIBL, higher breakdown voltages, and kink-free operation. Further SH SOI MOSFETs have been shown to exhibit reduced parasitic bipolar junction transistor effect in comparison to the homogeneously doped channel (conventional) SOI MOSFETs. Small-signal characterization on these devices shows higher ac transconductance, higher output resistance, and better dynamic intrinsic gain (g/sub m/R/sub o/) in comparison with the conventional homogeneously doped SOI MOSFETs. Also, the low drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance. The experimental results show that SH SOI MOSFETs exhibit a lower hot carrier degradation in small-signal transconductance and dynamic output resistance in comparison with conventional homogeneously doped SOI MOSFETs. From 2-D device simulations, the lower hot carrier degradation mechanism in SH SOI MOSFETs is analyzed and compared with the conventional SOI MOSFETs.

A small-signal RF model and its parameter extraction for substrate effects in RF MOSFETs

We propose a physically acceptable small-signal model incorporating substrate effects, in order to eliminate the severe frequency-dependence of the intrinsic drain-source resistance observed from a conventional model of RF Si MOSFETs. This model is based on the substrate network where a parallel RC circuit is connected in series with the drain junction capacitance. It is demonstrated that the substrate effects result in the frequency-dispersion of the effective drain-source resistance and capacitance below 10 GHz. An accurate extraction technique using a simple curve-fit approach is developed to determine substrate parameters directly, and their bulk voltage-dependencies are presented in detail. The validity of this model is partially proved by finding intrinsic parameters exhibiting frequency-independence up to 10 GHz. Better agreement with measured S-parameters is achieved by using the new substrate model rather than the conventional one, verifying the accuracy of the physical model and extraction technique.

MOSFETs with ultrashallow junction and minimum drain area formed by using solid-phase diffusion from SiGe

An advanced CMOS structure, in which a raised source/drain and contact windows formed over the field oxide, was fabricated. Ultrashallow junction formation using solid-phase diffusion from doped SiGe layers was used to fabricate MOSFETs. These MOSFETs demonstrated excellent short-channel characteristics and 70%-80%-reduced parasitic drain-junction capacitance. They have ultrashallow junctions with a depth of 25 nm and a low source/drain extension (SDE) resistance: 350 /spl Omega//sq (NMOSFETs) and 390 /spl Omega//sq (PMOSFETs). The isotropic diffused SDE structure was formed by using solid-phase diffusion, which could effectively form a shallow junction and a suitable overlap between gate and SDE. This structure results in good short-channel characteristics and high current drivability.

Unique extraction of substrate parameters of common-source MOSFETs

The unique extraction method of small-signal substrate parameters for MOSFETs is proposed. To cover the output resistance reduction at microwave frequency range, drain substrate resistance as well as drain junction capacitance is considered. Parasitic series resistances are extracted at the zero-gate-bias cold-FET condition using the asymptotic behavior of Z-parameters. The modeled S-parameters fit the measured ones well without any optimization after parameter extraction.

An asymmetrically doped buried-layer (ADB) structure for low-voltage mixed analog-digital CMOS LSI's

A new CMOS structure has been developed that is distinguished by its asymmetrically doped buried layer (ADB). This structure makes it possible to achieve high drain output resistance and high transconductance necessary for high-performance analog circuits with a low-voltage power supply. The ADB structure has a high-impurity-concentration pocket layer near the channel edge of the buried layer only on the source side and a low-impurity surface region through the channel. The source-side channel region determines the threshold voltage and the drain-side channel region absorbs the drain potential. The low-impurity surface region reduces impurity scattering and enables high transconductance. The fabricated ADB CMOS structure increased the drain output resistance, transconductance, and saturation current down to a 0.3-/spl mu/m channel length, as compared to a control structure. Furthermore, the drain junction capacitance was reduced because of the low impurity concentration beneath the drain region.

Quarter-micrometer SPI (Self-aligned Pocket Implantation) MOSFET's and its application for low supply voltage operation

A novel SPI (Self-aligned Pocket Implantation) technology has been presented, which improves short channel characteristics without increasing junction capacitance. This technology features a localized pocket implantation using gate electrode and TiSi/sub 2/ film as self-aligned masks. An epi substrate is used to decrease the surface impurity concentration in the well while maintaining high latch-up immunity. The SPI and the gate to drain overlapped structure such as LATID (Large-Angle-Tilt Implanted Drain) technology allow use of the ultra low impurity concentration in the channel region, resulting in higher saturation drain current at the same gate over-drive compared to conventional device. The carrier velocity reaches 8/spl times/10/sup 6/ cm/sec and subthreshold slope is less than 75 mV/dec, which can be explained by low impurity concentration in the channel and in the substrate. The small gate depletion layer capacitance of SPI MOSFET was estimated by C-V measurement, and it can explain high performance such as small subthreshold slope. On the other hand, the problem and the possibility of low supply voltage operation have been discussed, and it has been proposed that small subthreshold slope is prerequisite for low power device operated at low supply voltage. In addition, the drain junction capacitance of SPI is decreased by 65% for N-MOSFET's, and 69% for P-MOSFET's both compared with conventional devices. This technology yields an unloaded CMOS inverter of 48 psec delay time at the supply voltage of 1.5 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Inverter performance of 0.10 μm CMOS operating at room temperature

The switching performance of 0.10 /spl mu/m CMOS devices operating at room temperature has been discussed on the basis of both experimental and simulated results. The measured propagation delay time of a 0.10 /spl mu/m gate length CMOS has been quantitatively divided into intrinsic and parasitic components for the first time. The results have shown that the drain junction capacitance strongly affects the propagation delay time in the present 0.10 /spl mu/m CMOS. The switching performance of a 0.10 /spl mu/m ground rule CMOS has been simulated by using device parameters extracted from the experimental results. In the 0.10 /spl mu/m ground rule CMOS, it has been shown that an increase of the contact resistance will degrade the propagation delay time, which is one of the most essential problems in further device miniaturization. It has been also demonstrated that even if the specific contact resistance /spl rho//sub c/ is reduced to be less than 1/spl times/10/sup -7/ /spl Omega/ cm, further reduction of the gate overlap capacitance C/sub ov/ will be required to achieve the propagation delay time to be less than 10 ps in the 0.10 /spl mu/m ground rule CMOS at room temperature. >

High-performance 0.10- mu m CMOS devices operating at room temperature

The authors have fabricated 0.10- mu m gate-length CMOS devices that operate with high speed at room temperature. Electron-beam lithography was used to define 0.10- mu m polysilicon gate patterns. Surface-channel type p- and n-channel MOSFETs were fabricated using an LDD structure combined with a self-aligned TiSi/sub 2/ process. Channel doping was optimized so as to suppress punchthrough as well as to realize high transconductance and low drain junction capacitance. The fabricated 0.10- mu m CMOS devices have exhibited high transconductance as well as a well-suppressed band-to-band tunneling current, although the short-channel effect occurred somewhat. The operation of a 0.10- mu m gate-length CMOS ring oscillator has been demonstrated. The operation speed was 27.7 ps/gate for 2.5 V at room temperature, which is the fastest CMOS switching ever reported.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-performance dual-gate CMOS utilizing a novel self-aligned pocket implantation (SPI) technology

A self-aligned pocket implantation (SPI) technology is discussed. This technology features a localized pocket implantation using the gate and drain electrodes (TiSi/sub 2/ film) as well as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length L/sub g/ (the physical gate length) is 0.21 mu m for both N- and P-MOSFETs. A newly developed photoresist was used to achieve less than quarter-micrometer patterns. This process provides high punchthrough resistance and high current driving capability even in such a short channel length. The subthreshold slope of the 0.21- mu m gate length is 76 mV/dec for N-MOSFETs and 83 mV/dec for P-MOSFETs. The SPI technology maintains a low impurity concentration in the well (less than 5*10/sup 16/ cm/sup -3/). The drain junction capacitance is decreased by 36% for N-MOSFETs and by 41% for P-MOSFETs, compared to conventional LDD devices, which results in high-speed circuit operation. The delay time per stage of a 51-stage dual-gate CMOS ring oscillator is 50 ps with a supply voltage of 3.3 V and a gate length of 0.36 mu m, and 40 ps with a supply voltage of 2.5 V and a gate length of 0.21 mu m.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A self-aligned pocket implantation (SPI) technology for 0.2- mu m dual-gate CMOS

The self-aligned pocket implantation (SPI) technology developed features a localized pocket implantation using a gate electrode and TiSi/sub 2/ films as self-aligned masks. This process provides high punchthrough resistance and high current driving capability while suppressing the impurity concentration in the twin well. The drain junction capacitance is decreased by 30% for N-MOSFETs and by 49% for P-MOSFETs, compared to conventional LDD devices. It is found that a dual-gate CMOS device fabricated by the SPI technology achieves high circuit performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A high-speed logic LSI using diffusion self-aligned enhancement depletion MOS IC

This paper reports the design, fabrication, and characterization of a diffusion self-aligned enhancement depletion (DSA-ED) MOS IC. It is shown that using DSA structure, a short channel MOST with effective submicron channel length can be realized even by standard photolithographic techniques. High-speed characteristics of a DSA MOST, high gain factors, and small drain junction capacitance are described. The advantage of an ED configuration is discussed. To evaluate the basic performance of the gate, 19-stage ring oscillators with various device sizes have been developed. In the ring oscillator design, the high gain factors of the DSA MOST are fully utilized to minimize the device size and upgrade the performance and packing density. A propagation delay time of 0.65 ns, a power dissipation of 0.15 mW, a power delay product of 0.10 pJ at the supply voltage 2 V, and a packing density of 510 gate/mm/SUP 2/ have been obtained by the single-level metal interconnections of 7 /spl mu/m details. A 4-bit arithmetic logic unit (ALU) has been developed with the same design principle and device size to obtain the 2.9 ns/gate, 0.71 mW/gate performance at the supply voltage of 5 V and 141 gates/mm/SUP 2/ packing density.