Design of a 0.1 µm single halo (SH) thin film silicon-on-insulator (SOI) MOSFET for analogue applications

Abstract

In this paper, we propose a design of a 0.1 µm single halo (SH) thin film silicon-on-insulator (SOI) nMOSFET device for analogue and mixed signal applications. The single halo structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. The design methodology is based upon the improvement in the short-channel effects (SCE) and suppression of the kink. The device is optimized for various film thicknesses and different peak dopings. The position of the peak doping near the source is also an important parameter and hence, also needs to be optimized. The SH devices show better Vth–L roll-off, low drain induced barrier lowering, higher breakdown voltages and lower floating-body effects. The experimental results have shown the superior analogue performance of SH SOI MOSFETs. Also, the low drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance.