Double Heterojunction Bipolar Transistors Research Articles

High-performance uniform stepper-based InP double-heterojunction bipolar transistor (DHBT) on a 3-inch InP substrate

In this paper, InP Double-Heterojunction Bipolar Transistors (DHBTs) on a 3-inch InP substrate is demonstrated through stepper-based photolithography. The performance of the fabricated InP DHBTs such as DC characteristics, high-frequency characteristics, and uniformity of the 3-inch wafer is investigated to verify the stepper-based fabrication process. To improve the high-frequency characteristics, the self-aligned base-emitter contact is realized by using the high height-to-width ratio and vertical sidewall emitter profile of the Au electroplating process. The fabricated DHBTs with WE = 0.6 μm and LE = 15 μm exhibits current gain (β) = 50 at VCE = 1.0 V and an open-base common-emitter breakdown voltage (BVCEO) of 5.7 V at JC = 0.01 mA/µm2 and 7.5 V at JC = 0.1 mA/µm2, respectively. Moreover, the fabricated DHBTs with WE = 0.6 μm and LE = 15 μm show excellent fT of 244 GHz and fmax of 221 GHz at JC = 4.4 mA/μm2 and VCE = 1.6 V. In order to evaluate the uniformity of the fabricated DHBTs, we measure current gain (β) and high-frequency characteristics with WE = 0.6 μm and LE = 15 μm and the average values and standard deviation of the β, fT, and fmax are β = 49.3 ± 1.9, fT = 241.4 ± 3.8 GHz, and fmax = 221.5 ± 4.0 GHz, respectively. Thanks to the optimized stepper-based fabrication process, the fabricated InP DHBTs exhibit well-balanced high-frequency characteristics and excellent uniformity.

Effect of emitter-base spacer design on the performance of InP/GaAsSb/InP DHBTs grown by MOCVD

Effect of spacer layer design between InP emitter and GaAsSb base in InP/GaAsSb/InP double heterojunction bipolar transistors (DHBTs) grown by MOCVD was investigated. A very thin tensile-strained GaAs layer, or a thin GaInP layer, or combination of both was inserted between InP emitter and GaAsSb base to mitigate Sb segregation and/or eliminate electron pile-up between emitter and base. With a base sheet resistances of ∼1800 ohm sq−1 for all devices, DHBTs with a GaAs spacer, a GaInP spacer and the combination demonstrate a current gain of 24, 49 and 64, respectively. The conduct band discontinuity ΔEc at InP/GaAsSb interfaces and the current blocking effect are effectively eliminated by employing the combination of GaAs and GaInP layers.

InP DHBT Analytical Modeling: Toward THz Transistors

InP double heterojunction bipolar transistors (InP DHBT) are one of the key technologies considered for terahertz applications. Improvement of their frequency performance is challenging and strongly dependent on various parameters (manufacturing process, geometry, epitaxial structure). In this article, a novel method is developed to take into account these parameters and predict the frequency performance of the technology. This approach consists of rebuilding the S-parameter matrix of the small-signal model. Elements of the small signal model are identified, and their assessment is described in detail. Once calibrated with the present state-of-the-art device features, the model shows a good agreement with the measurements. Based on this result, analysis of the emitter and base technological features are performed along with optimizations of the vertical structure. Finally, the necessary optimizations for developing a terahertz transistor are detailed. This works provides guidelines for technological improvement and opens the way for designing transistors operating at frequencies above a terahertz.

Performance investigation of low-power flexible n-ZnO/p-CuO/n-ZnO heterojunction bipolar transistor: Simulation study

Oxide semiconductor-based heterojunction bipolar transistors are widely applicable in flexible, printable, and cost-effective circuit applications. Among earth-abundant metal oxides, zinc oxide and copper oxide inherently show n-type and p-type characteristics, respectively, and their electronic properties can be easily modified during the fabrication process. Accordingly, a planar-type HBT can be achieved by low-temperature growth of the metal-oxide layers on a flexible substrate without the need for further sophisticated processes. In this paper, a double heterojunction bipolar transistor (DHBT) comprised of ZnO layers serving as the emitter and collector regions, along with the CuO layer functioning as the base area is presented. Simulation results demonstrate that the proposed all-metal oxide transistor based on p-CuO/n-ZnO heterojunction enjoys low power consumption owing to the low threshold voltage. High-frequency characterization and DC analysis of the proposed NPN configuration are carried out using the ATLAS/SILVACO package. Our findings reveal that at the base-emitter voltage of 0.55 V, the current gain factor of the device reaches 155, which is larger than those reported in the literature. Furthermore, an ideality factor at the base-emitter voltage of 0.7 V was obtained for the collector-base and emitter-base junctions equal to 1.5 and 1.2, respectively.

GaN-Based Double-Heterojunction Bipolar Transistors With a Composition Graded p-InGaN Base

The influence of energy band structure on the electrical characteristics of GaN-based double-heterojunction bipolar transistors (DHBTs) has been studied through both simulation and fabrication. According to the simulation result, a novel DHBT structure with a composition graded base was grown and fabricated. A long minority carrier lifetime of 4.08 ns has been achieved for the composition graded p-InGaN base with a greatly improved material quality. The indium composition grading of the p-InGaN base layer combined with Si doping profile tuning for the collector layer was proposed to eliminate the energy barrier usually formed at the conventional GaN/InGaN/GaN base–collector (B–C) junction interface due to the band discontinuity and polarization effect. As a result, the as-fabricated DHBT presents a high intercept voltage of 225 V extracted from the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{I}_{\textit{C}}$</tex-math> </inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\text{CE}}$</tex-math> </inline-formula> curves and a high current gain of 49.

Transmitter and Receiver Circuits for a High-Speed Polymer Fiber-Based PAM-4 Communication Link.

A high data rate RF-DAC and a power detector (PD) are designed and fabricated in a 250 nm indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. A communication link using the Tx-Rx over polymer microwave fiber (PMF) is measured. The link consists of a pulse amplitude modulation (PAM) modulator and a PD as a demodulator, as well as a one-meter-long dielectric waveguide. The working frequency range of the complete link is verified to be 110–150 GHz. The peak output power of the PAM modulator is 5 dBm, and it has a −3 dB bandwidth of 43 GHz. The PD consists of a parallel connected common emitter configured transistor and a common base configured transistor to suppress the odd-order harmonics at the PD’s output, as well as a stacked transistor to amplify the output signal. Tx and Rx chips, including pads, occupy a total area of only 0.83 mm2. The PMF link can support a PAM-4 signal with 22 Gbps data transmission, and a PAM-2 signal with 30 Gbps data transmission, with a bit error rate (BER) of <10−12, with demodulation performed in real time. Furthermore, the energy efficiency for the link (Tx + Rx) is 4.1 pJ/bit, using digital data input and receiving PAM-2 output (5.6 pJ/bit for PAM-4).

K-Band Digital Power Amplifier Based on InP DHBT

Based on 0.7-μm indium phosphide (InP) double heterojunction bipolar transistor (DHBT) process, this paper designs a digital power amplifier (DPA) monolithic microwave integrated circuit. Digital-to-analog converter (DAC), modulation and power amplifier are integrated into the DPA, reducing losses and improving linearity of traditional radio frequency (RF) links. The test results show that the DPA can achieve an output power of 23-23.5 dBm and power added efficiency (PAE) of 21.5-23% within 19.2-21.2 GHz. And the mean squared error of normalized output voltage is 0.0158 at 20 GHz. Then, asymmetrical synthesis technology is used to improve the efficiency of DPA in non-full amplitude state. Simulation results of DPA demonstrate saturated output power of 23.5 dBm and the maximum PAE of 21.9% in 19-21 GHz. At 20 GHz, the PAE between full and half amplitude state is greater than 20%.

RF characterization of InP double heterojunction bipolar transistors on a flexible substrate under bending conditions

This letter presents the fabrication of InP double heterojunction bipolar transistors (DHBTs) on a 3-inch flexible substrate with various thickness values of the benzocyclobutene (BCB) adhesive bonding layer, the corresponding thermal resistance of the InP DHBT on flexible substrate is also measured and calculated. InP DHBT on a flexible substrate with 100 nm BCB obtains cut-off frequency f T = 358 GHz and maximum oscillation frequency f MAX = 530 GHz. Moreover, the frequency performance of the InP DHBT on flexible substrates at different bending radii are compared. It is shown that the bending strain has little effect on the frequency characteristics (less than 8.5%), and these bending tests prove that InP DHBT has feasible flexibility.

Fabrication and characteristics of double heterojunction bipolar transistor based on p-CuO/n-Si heterojunction

Fabrication and characteristics of double heterojunction bipolar transistor based on p-CuO/n-Si heterojunction

Temperature-dependent DC and small signal performance of InGaAs/InP DHBT

Temperature-dependent DC and small-signal analysis have been carried out on 0.7 μm × 15 μm InGaAs/InP double heterojunction bipolar transistors over a temperature range of 25 °C–125 °C by on-wafer S-parameter measurements up to 50 GHz. The thermal behavior of DC and equivalent circuit parameters along with their temperature coefficients were analyzed and reported for the first time using the same InP-based DHBT. Most of the DC parameters show a negative with temperature, for example the temperature coefficients of the VBE,on and VBC,on are −1.4 and −1.48 mV/°C, respectively. And the peak current gain declined from 44.04 to 36.09 with the temperature increased from 25 °C to 125 °C. On the other hand, most of the small-signal parameters show a positive trend with temperature, except for the intrinsic base resistance Rbi, intrinsic base–collector capacitance Cbc, intrinsic base–emitter capacitance Cbe, and common-base current transport factor α0. The results will provide valuable references and insights for future design optimizations of temperature susceptible circuits.

An electromagnetic simulation assisted small signal modeling method for InP double-heterojunction bipolar transistors

We present a convenient and practical electromagnetic (EM) assisted small-signal model extraction method for InP double-heterojunction bipolar transistors (DHBTs). Parasitic parameters of pad and electrode fingers are extracted by means of 3D EM simulation. The simulations with a new excitation scheme are closer to the actual on-wafer measurement conditions. Appropriate simulation settings are calibrated by comparing measurement and simulation of OPEN and SHORT structures. A simpler π-type topology is proposed for the intrinsic model, in which the base-collector resistance Rμ , output resistance R ce are deleted, and a capacitance C ce is introduced to characterize the capacitive parasitic caused by the collector finger and emitter ground bar. The intrinsic parameters are all extracted by exact equations that are derived from rigorous mathematics. The method is characterized by its ease of implementation and the explicit physical meaning of extraction procedure. Experimental validations are performed at four biases for three InGaAs/InP HBT devices with 0.8 × 7 μm, 0.8 × 10 μm and 0.8 × 15 μm emitter, and quite good fitting results are obtained in the range of 0.1–50 GHz.

Collector Series-Resistor to Stabilize a Broadband 400 GHz Common-Base Amplifier

The indium phosphide (InP) 130 nm double-heterojunction bipolar transistor (DHBT) offers milliwatts of output power and high signal amplification in the lower end of the terahertz frequency band when the transistor is used in a common-base configuration. Instrumentation can directly benefit from this technology by enabling the development of novel broadband sources or synthesizers that rely on our ability to amplify the signal over enormous bandwidths. However, the design of high gain and stable amplifiers presents many obstacles and limitations as we increase the bandwidth and the carrier frequency. Here, we show that adding a series resistor at the collector terminal of the common-base transistor prevents instabilities in the terahertz monolithic integrated circuit amplifier and increases its fractional bandwidth. Adopting this technique, we report a state-of-the-art broadband common-base amplifier that exhibits a minimum small-signal gain of 18.9 dB from 325 to 477 GHz. This amplifier presents the highest fractional bandwidth and gain above 300 GHz. Our work demonstrates the feasibility of high-performance amplifiers that address the need of future terahertz electronic systems.

A 32.2 GHz Full Adder Designed with TLE Method in a InP DHBT Technology

Ultra-high-speed full adder is the bottleneck in a tens of GHz Direct digital synthesizer (DDS). In this paper, a 32.2 GHz, 1bit full adder in a 0.7 μm InP double hetero-junction bipolar transistor (DHBT) technology is presented. In such a high-speed circuit, signal integrity is a crucial issue. Therefore, a transmission line equivalent (TLE) method is proposed. With the TLE method, the design of the full adder could be simplified with good accuracy. The synchronous latch is combined with adding operation to improve the calculation speed. A single-level parallel-gated circuit is designed using majority decision algorithm to reduce power consumption. Measurement results show that the maximum clock frequency of the full adder is 32.2-GHz, and the overall power consumption is 350 mW. The full adder is successfully adopted in a 17 GHz, 8 bit DDS which can synthesize sin-wave outputs from 66.41 MHz to 8.5 GHz in 66.41 MHz steps with an average Spurious-Free Dynamic Range (SFDR) of -18.1 dBc.

2D Cu9 S5 /PtS2 /WSe2 Double Heterojunction Bipolar Transistor with High Current Gain.

Bipolar junction transistor (BJT) as one important circuit element is now widely used in high-speed computation and communication for its capability of high-power signal amplification. 2D materials and their heterostructures are promising in building high-amplification and high-frequency BJTs because they can be naturally thin and highly designable in tailoring components properties. However, currently the low emitter injection efficiency results in only moderate current gain achieved in the pioneer researches, severely restraining its future development. Herein, it is shown that an elaborately designed double heterojunction bipolar transistor (DHBT) can greatly promote the injection efficiency, improving the current gain by order of magnitude. In this DHBT high-doping-density wide-bandgap 2D Cu9 S5 is used as emitter and narrow-bandgap PtS2 as base. This heterostructure efficiently suppresses the reverse electron flux from base and increase the injection efficiency. Consequently, the DHBT achieves an excellent current gain (β ≈ 910). This work systematically explores the electrical behavior of 2D materials based DHBT, and provides deep insight of the architecture design for building high gain DHBT, which may promote the applications of 2Dheterojunctions in the fields of integrated circuits.

Performance prediction of InP/GaAsSb double heterojunction bipolar transistors for THz applications

The intrinsic performance of “type-II” InP/GaAsSb double heterojunction bipolar transistors (DHBTs) toward and beyond THz is predicted and analyzed based on a multi-scale technology computer aided design modeling platform calibrated against experimental measurements. Two-dimensional hydrodynamic simulations are combined with 1D full-band, atomistic quantum transport calculations to shed light on future DHBT generations whose dimensions are decreased step-by-step, starting from the current device configuration. Simulations predict that a peak transit frequency fT,peak of around 1.6 THz could be reached in aggressively scaled type-II DHBTs with a total thickness of 256 nm and an emitter width WE of 37.5 nm. The corresponding breakdown voltage BVCEO is estimated to be 2.2 V. The investigations are put in perspective with two DHBT performance limiting factors, self-heating, and breakdown characteristics.

A 56–161 GHz Common-Emitter Amplifier with 16.5 dB Gain Based on InP DHBT Process

This paper presents a broadband amplifier MMIC based on 0.5 µm InP double-heterojunction bipolar transistor (DHBT) technology. The proposed common-emitter amplifier contains five stages, and bias circuits are used in the matching network to obtain stable high gain in a broadband range. The measurement results demonstrate a peak gain of 19.5 dB at 146 GHz and a 3 dB bandwidth of 56–161 GHz (relative bandwidth of 96.8%). The saturation output power achieves 5.9 and 6.5 dBm at 94 and 140 GHz, respectively. The 1 dB compression output power is −4.7 dBm with an input power of −23 dBm at 94 GHz. The proposed amplifier has a compact chip size of 1.2 × 0.7 mm2, including DC and RF pads.

Two-Dimensional Physical and Numerical Modelling of Copper (II)-Oxide/Silicon Hetero Junction Bipolar Transistor

Flexible and printed electronics have been widely applied due to their low cost, scalability in manufacturing, and usability in biosensors as well as wearable electronics. However, there are some limitations on fabrication of these devices including thermal limitations. Thermal constraints are of significance since ion implantation at high temperatures is one of the most important stages of fabrication; therefore, despite these limitations, fabrication of flexible BJT is practically impossible through conventional methods. In this study, copper oxide was used for the collector and emitter area of Double Heterojunction Bipolar Transistor (DHBT) due to the low-temperature deposition of copper oxide through the printing method, and the ability to adjust the doping according to the deposition conditions. DC and high-frequency specifications of two transistors with PNP and NPN structures were simulated using two-dimensional semiconductor simulator atlas module of SILVACO software.

Towards Monolithic Indium Phosphide (InP)-Based Electronic Photonic Technologies for beyond 5G Communication Systems

This review paper reports the prerequisites of a monolithic integrated terahertz (THz) technology capable of meeting the network capacity requirements of beyond-5G wireless communications system (WCS). Keeping in mind that the terahertz signal generation for the beyond-5G networks relies on the technology power loss management, we propose a single computationally efficient software design tool featuring cutting-edge optical devices and high speed III–V electronics for the design of optoelectronic integrated circuits (OEICs) monolithically integrated on a single Indium-Phosphide (InP) die. Through the implementation of accurate and SPICE (Simulation Program with Integrated Circuit Emphasis)-compatible compact models of uni-traveling carrier photodiodes (UTC-PDs) and InP double heterojunction bipolar transistors (DHBTs), we demonstrated that the next generation of THz technologies for beyond-5G networks requires (i) a multi-physical understanding of their operation described through electrical, photonic and thermal equations, (ii) dedicated test structures for characterization in the frequency range higher than 110 GHz, (iii) a dedicated parameter extraction procedure, along with (iv) a circuit reliability assessment methodology. Developed on the research and development activities achieved in the past two decades, we detailed each part of the multiphysics design optimization approach while ensuring technology power loss management through a holistic procedure compatible with existing software tools and design flow for the timely and cost-effective achievement of THz OEICs.

A Novel Design Method of SOF for InP DHBT ECL and CML Static Frequency Dividers

In this letter, we present a novel analysis and design approach of self-oscillation frequency (SOF) for 0.8-μm indium phosphide (InP) double-heterojunction bipolar transistor (DHBT) emitter-coupled logic (ECL) and current-mode logic (CML) static frequency dividers. SOF of ECL and CML dividers is designed to be the maximum value after theoretical analysis and multiparameter optimization. The results show that the SOF of the ECL and CML divider is 62 and 37.5 GHz, respectively. With sinusoidal waveform input, the operating frequency range of the ECL divider is from 0.1 to 65 GHz, and CML is from 0.1 to 55 GHz, while the cut-off frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> is 150 GHz. For ECL, the f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> utilization of SOF (SOF /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) is 0.413, and CML is 0.25. These are the maximum SOF results that can be designed for the two dividers under the same design conditions.

A wideband mono-bit digital receiver circuit using InP/CMOS 3D heterogeneous integration

A mono-bit digital receiver circuit for instantaneous frequency measurement is presented. The circuit is co-designed with Indium Phosphide Double Heterojunction Bipolar Transistor and complementary metal oxide semiconductor (CMOS) devices. The chip is fabricated by InP/CMOS three-dimensional (3D) heterogeneous integration using the wafer-level bonding technique. The measurable signal frequency within + 15 to − 25 dBm power is up to 7.5 GHz with a 14-GHz clock. Compared to an integrated circuit (IC) with a traditional InP or CMOS technologies, the proposed chip could benefit from both InP and CMOS technology. In the heterogeneous integration, InP devices provide high operating frequency, broad signal bandwidth, and large input signal dynamic range, while CMOS devices achieve complex function with low power consumption. In this way, the system FoM is improved for a mono-bit digital receiver while the system power consumption is kept the same. This work also shows the great potential of the 3D heterogeneous integration for the high-performance mixed-signal and multifunction radio-frequency ICs.