Abstract
In this letter, we present a novel analysis and design approach of self-oscillation frequency (SOF) for 0.8-μm indium phosphide (InP) double-heterojunction bipolar transistor (DHBT) emitter-coupled logic (ECL) and current-mode logic (CML) static frequency dividers. SOF of ECL and CML dividers is designed to be the maximum value after theoretical analysis and multiparameter optimization. The results show that the SOF of the ECL and CML divider is 62 and 37.5 GHz, respectively. With sinusoidal waveform input, the operating frequency range of the ECL divider is from 0.1 to 65 GHz, and CML is from 0.1 to 55 GHz, while the cut-off frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> is 150 GHz. For ECL, the f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> utilization of SOF (SOF /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) is 0.413, and CML is 0.25. These are the maximum SOF results that can be designed for the two dividers under the same design conditions.
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