Double Edge-triggered Flip-flops Research Articles

Probability Driven Double-Edge Triggered Multibit Flip Flop and Clock Gating Integration

Abstract: The project delves into the using of Double Edge-Triggered Multi-Bit Flip-Flops (DETMBFFs) alongside Data Driven Clock Gating (DDCG) techniques to bolster power efficiency in digital circuit designs. DETMBFFs enable the data Capture on Both Up and Down Swings of a clock, optimizing throughput while conserving power. By grouping multiple flip-flops and employing a shared clock driver, DETMBFFs minimize redundant clock signals and reduce energy usage. The integration of DDCG selectively disables clock signals based on data activity, further enhancing power efficiency. A novel algorithm, grounded in the ratio of the data to clock toggling and probability-driven grouping of flip-flops within DETMBFFs, is developed to optimize power consumption. Through implementation using Xilinx software tool, the combined approach achieves remarkable power savings ranging from 17% to 23%. This creative approach not only enhances power efficiency but also maintains design integrity,making it a compelling solution for low-power design challenges in digital systems.

A 100-MHz 3.352-mW 8-bit shift register using low-power DETFF using 90-nm CMOS process

ABSTRACT By keeping the very same transmission rate, a scheme is provided by DETFF (double-edge triggered flip-flops) for power dissipation reduction. As a result, they are suitable for use as shift registers. This investigation discussed various previous DETFF designs and demonstrated a new DETFF circuit applied to construct an 8-bit low-power shift register. This study makes a significant contribution by using two parallel data paths that operate in a single clock’s opposing phases where an inverted input trigger is unnecessary. TSMC 90-nm complementary metal-oxide semiconductor (CMOS) technology was used to implement the proposed shift register. Comparing the proposed DETFF with prior works, it has fewer transistor counts since the negated input trigger and auxiliary devices were removed, resulting in lower area cost and lower power dissipation. At 100 MHz clock frequency and lower supply voltage of 1.0 V, it demonstrates a power consumption of 3.352 mW on silicon, making it suitable for low-power applications. Lastly, it has the best performance compared with prior works speaking of larger scale, as demonstrated by the chip’s functionality and jitter measurement at the maximum frequency of 200 MHz.

Anti-interference low-power double-edge triggered flip-flop based on C-elements

When the input signal has been interfered and glitches occur, the power consumption of Double-Edge Triggered Flip-Flops (DETFFs) will significantly increase. To effectively reduce the power consumption, this paper presents an anti-interference low-power DETFF based on C-elements. The improved C-element is used in this DETFF, which effectively blocks the glitches in the input signal, prevents redundant transitions inside the DETFF, and reduces the charge and discharge frequencies of the transistor. The C-element has also added pull-up and pull-down paths, reducing its latency. Compared with other existing DETFFs, the DETFF proposed in this paper only flips once on the clock edge, which greatly reduces the redundant transitions caused by glitches and effectively reduces power consumption. This paper uses HSPICE to simulate the proposed DETFF and other 10 DETFFs. The findings show that compared with the other 10 types of DETFFs, the proposed DETFF has achieved large performance indexes in the total power consumption, total power consumption with glitches, delays, and power delay product. A detailed analysis of variance indicates that the proposed DETFF features less sensitivity to process, voltage, temperature, and Negative Bias Temperature Instability (NBTI)-induced aging variations.

A novel approach for the design of low-power pipelined synchronous systems operating in double–edge of the clock

The continuous search for higher performances and low power dissipation on digital systems shows to be critical. The pipeline control is a good alternative for achieving good results, but the activity of the clock is responsible for the high consumption of 15–45% of the total circuit energy. Decreasing the clock activity leads not only to a reduction of this consumption but also to a reduction of noise and electromagnetic interference. An interesting approach to achieve this goal is the design of synchronous digital systems that operate in both edges of the clock signal (double-edge triggered – DET), allowing a reduction of 50% in the operating frequency while maintains the same data processing rate. As we know, the use of double-edge triggered flip-flops (DET-FF) leads to some main drawbacks. Then, in this paper, we propose a novel method that allows synthesizing synchronous digital systems with pipeline control. Such control operates in both edges of the clock using only standards flip-flops (single-edge triggered flip-flops-SET-FF) as components of the state memories. The method was validated for a well-known example (second order differential equation solver), and it was applied to a set of 5 well-known benchmarks, showing a mean reduction of 53% in latency time when compared to conventional methods working at the same frequency (in the case 50MHZ). We achieved an average reduction of 10% in latency time when the operating frequency of our projects was reduced to 25MHZ and compared to conventional ones at 50MHZ. The proposed method leads to a mean reduction of 45% in dynamic power consumption when compared to conventional ones. These results, although presenting a minimum area penalty, show a high potential of practical implementations focusing on low-power and high performances.

Robust Design of a Dual Edge Triggered Flip Flop at Low Power for High Speed Applications

The logic construction of a double-edge-triggered (DET) flipflop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 micron technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time and higher maximum data rate compared to other existing CMOS DET flip flops. By simulating and comparing the proposed DET flip-flop with the other designs present, it is shown that the proposed DET flip-flop reduces power dissipation while keeping the same date rate and can be used for high speed applications.

English

A low power dual edge triggered flip flop based on a signal feed through scheme is presented. The power consumption is the major problem in circuit design. The proposed deign reduces power and delay compared to explicit pulse triggered flip flop. Reducing the number of transistor in the stack and increasing the number of charge path leads to higher operational speed compared to others flip-flops. Double-edge-triggered flip flops (DETFFs) are recognized as power-saving flip flops. The dual edge triggered design operates in a low voltage range and hence it is suited for low voltage application. This flip flop uses weak feedback transistor but without static power consumption. This reduces leakage current and thus saves the power. By using low clock frequency high throughput can be achieved. The simulation is done using Tanner EDA Tool v14 with CMOS 90nm technology.

Asynchronous Data Sampling Within Clock-Gated Double Edge-Triggered Flip-Flops

For synchronous designs, a large portion of the total power consumption of the integrated circuit (IC) is due to the storage elements and the clock distribution. Energy efficiency from the clock elements plays a critical role in low-power circuit design. One technique for efficiency is the use of double edge-triggered flip-flops (DETFFs), since they can maintain the same throughput as single edge-triggered flip-flops (SETFFs) while only using half of the clock frequency. Clock gating is another well-accepted technique to reduce the dynamic power of idle modules or idle cycles. However, incorporating clock gating with DETFFs to further reduce dynamic power consumption introduces an asynchronous data sampling (i.e., a change in output between clock edges) that was not addressed in previous research. This asynchronous data sampling is explored in detail in this paper by analyzing the mechanisms of several different clock-gated DETFFs. Three special clock-gating strategies are evaluated to mitigate this issue in DETFFs. Each of these three solutions has limitations, and the respective tradeoffs are discussed.

Low-power and area-efficient 9-transistor double-edge triggered flip-flop

Double-edge triggered flip-flops offer a solution to clock power reduction by lowering the clock frequency and maintaining the same data rate. A compact 9-transistor double-edge triggered flip-flop for reducing flip-flop power is proposed. A combination of a selective swing-based partial transmission gate (TG) approach and multi-Vt transistors is used to make it area and power-efficient. The selective swing-based transmission gate approach reduces the transistor count, and the selective use of low-Vt transistors overcomes the effect of any intermediate low swing voltage levels in the circuit due to a partial TG approach. Low transistor count reduces capacitive load of the dynamic power component, and selective use of low-Vt transistors improves circuit performance as well as reduces power-delay product. The proposed circuit is implemented in the Samsung 130nm 1P6M Multi-Vt CMOS process technology and simulated for various PVT conditions. Results show that the power consumption of the circuit is reduced by 9.58% and energy reduced by 14.2% with a 5.12% improvement in speed for a slow process when compared to the previous techniques.

A Low Power Delay Buffer Using Gated Driver Tree

This project presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. A novel gated- clock-driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-driver-tree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power. The simplest way to implement a delay buffer is to use shift registers. If the buffer length N is and the word-length is b , then a total of Nb DFFs are required, and it can be quite large if a standard cell for DFF is used. In addition, this approach can consume huge amount of power since on the average Nb/2 binary signals make transitions in every clock cycle. As a result, this implementation is usually used in short delay buffers, where area and power are of less concern. Although some power is indeed saved by gating the clock signal in inactive blocks, the extra R-S flip- flops still serve as loading of the clock signal and demand more than necessary clock power. We propose to replace the R-S flip-flop by a C-element and to use tree-structured clock drivers with gating so as to greatly reduce the loading on active clock drivers. Additionally, DET flip-flops are used to reduce the clock rate to half and thus also reduce the power consumption on the clock signal. The proposed ring counter with hierarchical clock gating and the control. Each block contains one C-element to control the delivery of the local clock signal CLK to the DET flip-flops, and only the CKE signals along the path passing the global clock source to the local clock signal are active. The gate signal (CKE) can also be derived from the output of the DET flip-flops in the ring counter.

Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop

In this paper, a new technique for implementing low-energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch-sharing scheme to reduce the number of clocked transistors in the design. The newly proposed design also employs conditional discharge and split-path techniques to further reduce switching activity and short-circuit currents, respectively. As compared to the other state of the art double-edge triggered flip-flop designs, the newly proposed CBS_ip design has an improvement of up to 20% and 12.4% in view of power consumption and PDP, respectively

XNOR-based double-edge-triggered flip-flop for two-phase pipelines

The conventional approach of double-edge-triggered flip-flops (DET-FFs) is to have two similar edge-triggered latches. And the achieved faster speed is at the cost of double chip area and complex logic structure. By contrast, the XNOR-based approaches is difficult to reach the speed demand due to the delay of the XNOR -based clock generator. This paper proposes a new designed DET-FF based on an alternative XNOR gate. By utilizing the sensitivity to the driving capacity of the previous stage, we use this simplified XNOR gate as a pulse-generator. A modified transparent latch following the pulse-generator acts as an XNOR-based DET-FF, which accomplishes the almost same speed and less power dissipation as compared with two conventional DET-FFs under HSPICE simulation. We also implemented the XNOR-based DET-FF in a two-phase-pipeline system, and the HSPICE simulation in the TSMC 0.25 um CMOS process shows our proposed DET-FF is much faster than those two conventional DET-FFs.

A static differential double edge-triggered flip–flop based on clock racing

In this paper, a double edge-triggered (DET) flip–flop is proposed, suitable for high-performance and low-power applications. The presented flip–flop has differential structure and provides static operation. The double edge triggering operation is achieved, by generating a narrow pulse immediately after each clocking edge, which is used to set the flip–flop in the transparent phase. The narrow pulse generation technique is based on a clock racing methodology. Compared to existing DET flip–flops, the proposed DET flip–flop results in significant delay and power gains, but keeps the total transistor count low. By applying the narrow pulse to more than one similar adjacent DET flip–flops, we can further reduce the power and the transistor count.

Analysis of power dissipation in double edge-triggered flip-flops

A comprehensive analysis of double edge triggered (DET) flip-flops' power dissipation, taking into account input signal statistics, is presented in this paper. It is shown that using DET instead of a single edge-triggered flip-flop may result in significant energy savings if the input signal has reduced activity. On the other hand, the high switching rate of DET internal nodes may result in larger power dissipation if the input signal has a high transition probability or significant glitching.

High performance double edge-triggered flip-flop using a merged feedback technique

Double edge-triggered flip-flops (DETFFs) use both edges of the clock to latch data and hence can lead to significant power saving over single edge-triggered flip-flops for a fixed data rate. However, existing DETFF implementations suffer from the problems of charge sharing, charge coupling, incomplete voltage swing, poor voltage scaling properties and excessive power dissipation. A new DETFF is proposed, which does not suffer from any of these problems and can operate at a clock speed which is 1.33 times that of the best double edge-triggered flip-flop available today. With reduced supply voltages, this flip-flop results in lower power dissipation and maintains a comparable performance to, if not better than, existing DETFFs.

Design of high performance double edge-triggered flip-flops

A methodology for constructing double edge-triggered flip-flops (DETFFs) from existing latches, which removes the need for complete flip-flops or the presence of clocked nodes in the combining section is presented. The application of this methodology to designing DETFFs based on latches constructed from pass transistor/transmission gates, true single-phase clocked structures, and differential logic is investigated. The resulting DETFFs deliver high performance and do not suffer from the problems of charge sharing, charge coupling, reduced voltage swing, poor supply voltage scaling properties, and excessive power dissipation plaguing existing DETFFs.

Low power double edge-triggeredflip-flop using one latch

Low power double edge-triggered flip-flop using one latch A low power double edge-triggered (DET) flip-flop using a single latch is presented. In the proposed circuit, data are sampled into the latch during a short transparency period for each edge of the clock signal. The proposed flip-flop requires small silicon area and has lower power dissipation with respect to previously reported DET flip-flops.

Altering transistor positions: impact on the performance and power dissipation of dynamic latches and flip-flops

Floating nodes is a point of concern in dynamic latches and flip-flops. When floating these nodes are extremely susceptible to noise: their voltage level may get distorted owing to charge coupling with other nodes. The current approach to this problem is to convert these dynamic circuits into semistatic/static ones by using feedback transistors. Increased robustness in semistatic circuits comes at the expense of decreased performance and increased power dissipation. It is demonstrated that simply altering the relative positions of transistors can protect floating nodes from some of the sources of charge coupling. The simulation results show that for a 0.8 /spl mu/m process the proposed technique leads to a significant improvement in both the speed and power dissipation of the true single-phase clocking single and double edge-triggered flip-flops without compromising chip area.

Low-power double-edge triggered flipflop

Low-power double-edge triggered flipflops are presented using weak feedback transistors which allow purely n-type transmission gates, but without static-power consumption. The switching capacitance of the weak transistors is minimised by using permanently ON transistors in series as resistive devices. Both static and semi-static circuits are presented.

Reduced implementation of D-type DET flip-flops

One of the main disadvantages of using D-type double-edge triggered flip-flops (DET-FFs) in VLSI system design is the number of transistors required. Two new DET-FF circuits (one static, the other dynamic) are proposed in which the number of transistors is reduced to a number similar to that for classic single-edge triggered flip-flops (SET-FFs). Both new circuits not only behave correctly when operated at high frequency but also offer a good level of immunity to metastability problems (static) and race problems (dynamic), as well as presenting a simple straightforward layout. These considerations offer wider practical and economic applications for the use of DET-FFs in VLSI system design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>