Altering transistor positions: impact on the performance and power dissipation of dynamic latches and flip-flops

Abstract

Floating nodes is a point of concern in dynamic latches and flip-flops. When floating these nodes are extremely susceptible to noise: their voltage level may get distorted owing to charge coupling with other nodes. The current approach to this problem is to convert these dynamic circuits into semistatic/static ones by using feedback transistors. Increased robustness in semistatic circuits comes at the expense of decreased performance and increased power dissipation. It is demonstrated that simply altering the relative positions of transistors can protect floating nodes from some of the sources of charge coupling. The simulation results show that for a 0.8 /spl mu/m process the proposed technique leads to a significant improvement in both the speed and power dissipation of the true single-phase clocking single and double edge-triggered flip-flops without compromising chip area.