Probability Driven Double-Edge Triggered Multibit Flip Flop and Clock Gating Integration

Abstract

Abstract: The project delves into the using of Double Edge-Triggered Multi-Bit Flip-Flops (DETMBFFs) alongside Data Driven Clock Gating (DDCG) techniques to bolster power efficiency in digital circuit designs. DETMBFFs enable the data Capture on Both Up and Down Swings of a clock, optimizing throughput while conserving power. By grouping multiple flip-flops and employing a shared clock driver, DETMBFFs minimize redundant clock signals and reduce energy usage. The integration of DDCG selectively disables clock signals based on data activity, further enhancing power efficiency. A novel algorithm, grounded in the ratio of the data to clock toggling and probability-driven grouping of flip-flops within DETMBFFs, is developed to optimize power consumption. Through implementation using Xilinx software tool, the combined approach achieves remarkable power savings ranging from 17% to 23%. This creative approach not only enhances power efficiency but also maintains design integrity,making it a compelling solution for low-power design challenges in digital systems.