Design and implementation of adaptive clock gating technique with double edge triggered flip flops

Abstract

The power consumption of circuit design finds how much energy is consumed per operation. The large portion of the power consumption in integrated circuit is mostly depends on storage element and clock signal distribution. A clock is used to ensure that all operation occur at the same instant. The important technique for efficiency is the use of double edge triggered flip fops (DETFFS). Which can be maintaining the same throughput of single edge triggered flip fops while using the half of the clock frequency. Clock gating is another good technique to reduce the dynamic power consumption. However incorporating the clock gating technique with double edge triggered flip fops further reduce the dynamic power consumption which creates the asynchronous sampling. It can be avoided by changing the D flip flop master latch circuit parameter.