Design of delay buffer using shift registers for asynchronous data sampling

Abstract

Due to the storage elements and the clock distribution in synchronous design there is a large power consumption of the integrated circuit (IC). Energy efficiency from the clock elements plays a critical role in low-power circuit design. The double edge-triggered flip-flops (DETFFs) are used to increase the efficiency, which uses half the frequency and can maintain the same throughput as single edge-triggered flip-flops. The technique used to reduce the dynamic power of idle modules or idle cycles is clock gating. Clock gating can be used along with DETFFs to further reduce dynamic power consumption introduces an asynchronous data sampling. A solution has been provided to avoid the asynchronous sampling problem in clock-gated DETFFs. The proposed work is the delay buffer implemented by shift registers can be used as an application for asynchronous data sampling.