Channel Doping Concentration Research Articles

Advanced Short-Channel-Effect Modeling With Applicability to Device Optimization—Potentials and Scaling

Silicon-thickness scaling has been used as the main parameter for short-channel-effect (SCE) reduction. Nevertheless, SCEs are still present in advanced thin-layer MOSFETs. Here, for enlarging the insight into SCE suppression, a new compact model is developed based on the SCE origin, which is demonstrated to be the potential distribution at the contact/channel junctions. In addition, it is shown that the potential distribution along the MOSFET channel can be modeled by overlapping potentials coming from the source and drain sides. The developed compact model is verified with leading-edge multi-gate MOSFETs, further demonstrating that device optimization with SCE suppression becomes possible due to the accurate reproduction of the device characteristics. The model validation is done with 2-D device simulations for different channel lengths, oxide, and silicon thicknesses as well as channel-doping concentration, for which an accurate compact-model reproduction is achieved. In addition, the general properties of the potential-based SCE model are extended to other MOSFET device structures.

A 800 V β‐Ga2O3 Metal–Oxide–Semiconductor Field‐Effect Transistor with High‐Power Figure of Merit of Over 86.3 MW cm−2

Herein, a high‐performance β‐gallium oxide (β‐Ga2O3) metal–oxide–semiconductor field‐effect transistor (MOSFET) on sapphire substrate with a high breakdown voltage of more than 800 V and a high‐power figure of merit of more than 86.3 MV cm−2 is demonstrated. The atomic force microscopy (AFM) image and Raman peaks that are first characterized to ensure a nanomembrane with high quality are used for the device fabrication. A saturation drain current of 231.8 mA mm−1, an RON,sp of 7.41 mΩ cm2, an ON/OFF ratio of 108, and a subthreshold swing of 86 mV dec−1 are obtained at a channel doping concentration of 4.47 × 1017 cm−3 and a source‐to‐drain distance of 11.4 μm. Furthermore, a high breakdown voltage over 800 V is also achieved, corresponding to a record‐high direct current (DC) power figure of merit of 86.3 MW cm−2. Technology computer aided design (TCAD) simulation is also performed to extract the distribution of the electric field along the β‐Ga2O3 channel surface.

Optimization of Electrical Parameters of Pocket Doped SOI TFET with L Shaped Gate

In this work, a pocket doped hetero source Silicon-on-insulator Tunneling Field Effect Transistor (SOI-TFET) with L shaped gate including back gate is proposed. The operation of this device is primarily dependent on band to band tunneling. Performance of a p-i-n TFET (proposed structure 1) is examined against the SOI double gate TFET (proposed structure 2). A brief investigation of the proposed device has been done by drain bias variation, EOT scaling, channel length modulation, pocket thickness variation, substrate dimension scaling and back gate voltage variation using Sentaurus TCAD software. The device performance is optimized for different source, drain, channel and pocket doping concentration and work function tuning of the front gate. It provides a high Ion/Ioff ratio, best reported 3.326 × 1011; steep Subthreshold Swing, SS best reported point SS 22.21 mV/decade (2 nm gate oxide) and average SS 31.74 mV/decade (3 nm gate oxide). The ON current is found to be high i.e. in the orders of mA. The proposed device is immune to short channel effects like DIBL and channel length modulation.

Demonstration and analysis of channel mobility, trapped electron density and Hall effect at SiO2/SiC (03) interfaces

Low interface state density (Dit) and high field-effect mobility (μfe) at SiO2/4H-SiC (03) Metal-oxide-semiconductor (MOS) interfaces are known. In order to understand the behavior and the scattering mechanisms induced electrons in more detail, we fabricated the Hall-bar lateral MOSFETs on the 4H-SiC (03) substrate with various channel doping concentrations and evaluated the trapped electron densities and the Hall mobilities by split capacitance–voltage and Hall-effect measurements. Our results demonstrated that more than 80% of the induced electrons at the SiO2/4H-SiC MOS (03) interfaces contribute to the current conduction as the free electrons. The majority of the electron traps seemed to be located mainly at the edge of the conduction band because the trapped electron density increased around the threshold voltage and was saturated in the high gate voltage region.

Impact of fin shapes and channel doping concentrations on the operation of junctionless transistors

The influence of variations in the Si fin shape on the electrical properties of junctionless transistors (JLTs) was investigated through two-dimensional Poisson equation numerical simulations at different doping concentrations. Stronger gate coupling in a triangular fin channel was observed, arising from suppression of the variation in the conduction threshold voltage with increasing doping concentration, compared to JLTs with rectangular fin channels. The potential distribution in the channel cross-section shows a less varied potential at the bottom of a triangular channel than at the bottom of a rectangular channel, and supports the result that triangular channels are less sensitive to variations in channel doping concentration.

Random dopant fluctuations impact reduction in 7 nm bulk-FinFET by substrate engineering

Currently, fin-field-effect-transistors (FinFETs) are used at 7 nm technology node, in order to avoid parasitic leakage channel under the controlled channel punch-through-stopper (PTS) doping is used with the bulk Silicon substrate (PTS-Si substrate). The dopants from PTS doping enters into the channel during the annealing process and increases channel doping level. The increased doping concentration in channel causes undesirable effects such as reduction in channel mobility and increase in random-dopant-fluctuations (RDFs). Using a silicon-on-insulator (SOI) substrate is a costlier solution, this work presents super-steep-retrograde-silicon (SSR-Si) substrate as a better solution for this problem. In this work, the SSR-Si substrate is achieved by placing lightly doped 10 nm thick SSR-buffer layer (silicon) on top of PTS-Si substrate. This SSR-buffer layer captures dopants intruding from PTS doping into channel thereby achieves SSR doping profile in the channel. The results show SSR-Si substrate reduces the RDF induced threshold variations by 50%, it also provides better DC and RF/analogue metrics than PTS-Si substrate and comparable with SOI substrate.

Random dopant fluctuations impact reduction in 7 nm bulk-FinFET by substrate engineering

Currently, fin-field-effect-transistors (FinFETs) are used at 7 nm technology node, in order to avoid parasitic leakage channel under the controlled channel punch-through-stopper (PTS) doping is used with the bulk Silicon substrate (PTS-Si substrate). The dopants from PTS doping enters into the channel during the annealing process and increases channel doping level. The increased doping concentration in channel causes undesirable effects such as reduction in channel mobility and increase in random-dopant-fluctuations (RDFs). Using a silicon-on-insulator (SOI) substrate is a costlier solution, this work presents super-steep-retrograde-silicon (SSR-Si) substrate as a better solution for this problem. In this work, the SSR-Si substrate is achieved by placing lightly doped 10 nm thick SSR-buffer layer (silicon) on top of PTS-Si substrate. This SSR-buffer layer captures dopants intruding from PTS doping into channel thereby achieves SSR doping profile in the channel. The results show SSR-Si substrate reduces the RDF induced threshold variations by 50%, it also provides better DC and RF/analogue metrics than PTS-Si substrate and comparable with SOI substrate.

Investigation of Nitrous Oxide Nitridation Temperatures on P-Type Pi-Gate Poly-Si Junctionless Accumulation Mode TFTs

In this paper, the influence of nitrous oxide (N2O) nitridation temperatures on p-type Pi-gate (PG) poly-Si junctionless accumulation mode (JAM) TFTs is experimentally investigated. The tetraethoxysilane (TEOS) gate oxide quality for PG JAM TFTs can be significantly improved by increasing N2O nitridation temperatures ( $T_{N}$ ) from 700 °C to 800 °C in N2O ambient, resulting in the improvement of average subthreshold swing (A.S.S.), increase of on current ( ${\text{I}}_{\text{ON}}$ ), and enhancement of TEOS gate oxide breakdown ${E}$ -field ( ${E} _{\text {OBD}}$ ). PG JAM TFTs by means of a proper channel doping concentration ( $N_{\text {ch}}= {5} \times {10}^{18}$ cm $^{-3}$ ) and a suitable $T_{N}$ (800 °C) exhibit a steep A.S.S. ~96 mV/dec. and a large ${E} _{\text {OBD}} {\sim }12.1$ MV/cm.

Modeling the threshold voltage variation induced by channel random dopant fluctuation in fully depleted silicon-on-insulator MOSFETs

In nanoscale fully depleted silicon-on-insulator (FD-SOI) MOSFETs, the standard deviation of threshold voltage (σVth) caused by random dopant fluctuation (RDF) is an important parameter to predict the performance of transistors and circuits. In this paper, an analytic model of σVth considering both the dopant “number” and dopant “position” fluctuation in channels is proposed. A new model of σVth,num caused by “number” is given and the method of obtaining the “position” influence ratio Rp is discussed in this paper. Moreover, the simulation methods are analyzed in detail. The calculated σVth values in FD-SOI MOSFETs are compared with the Sentaurus TCAD simulation results at different channel lengths, channel doping concentrations, SOI film thicknesses, front gate oxide thicknesses, and buried-oxide thicknesses. The comparison shows that the proposed model matches well with the obtained numerical simulation results.

Effect of OFF-state stress on reliability of nMOSFET in SWD circuits of DRAM

In this paper, we investigate the effect of OFF-State stress occurring at nMOSFET in a sub word-line driver (SWD) circuit under the DRAM operating conditions. Through the experimental study, we found that the increase in the number of OFF-carriers by the OFF-State stress caused the significant decrease of ON-current (Ion). During the initial period, the OFF-State stress generated the positive oxide charges (Qox) and the interface traps (Nit), which caused the increase of OFF-current (Ioff) and the decrease of Ion. After the degradations were saturated, both the Ion and Ioff decreased due to the increase in the number of OFF-carriers. Also the OFF-State degradation increased with decreasing source voltage, channel doping concentration, and channel length. Furthermore, the sensitivity of the OFF-State degradation to body bias (Vb) increased with scaling the oxide thickness (Tox). These new observations suggest that the OFF-State degradation for core transistors can impose the significant limitation on the SWD circuit design in DRAM such as scaling of dimension and determination of word-line voltage.

Exploring the Threshold Voltage Characteristics and Short Channel Behavior of Gate Engineered Front Gate Stack MOSFET with Graded Channel

The present work focuses on formulating a detailed two dimensional analytical model of the proposed Triple Metal Stacked Front Gate Oxide Double Gate MOSFET with step graded channel (GC-TMDG MOSFET) incorporating the dual benefits of gate and channel engineering techniques. Proper choice of a lower work function metal and lower channel doping concentration near the drain end serves the purpose of suppressing the unwanted impact ionization induced Hot Carrier Effects (HCEs) at the drain side of a nano-dimensional device, thereby making it a suitable ultra low dimensional device for future nano generation. The results obtained from analytical modeling depict a detailed comparative analysis of the proposed GC-TMDG MOSFET with its graded channel DG MOSFET counterpart to substantiate the improved performance of the proposed device in terms of surface potential, electric field, threshold voltage roll off, Drain Induced Barrier Lowering and drain current behavior. The analytical results are found to be in good agreement with 2D ATLAS simulator data, thereby validating our analytical model.

Effects of Metal–Interlayer–Semiconductor Source/Drain Contact Structure on n-Type Germanium Junctionless FinFETs

In this paper, the effects of a metal–interlayer–semiconductor (MIS) source/drain (S/D) structure with a heavily doped interlayer on enhancement-mode n-type germanium (Ge) junctionless FinFETs (JLFETs) are demonstrated via 3-D technology computer aided design simulation. N-type Ge JLFETs using metal–semiconductor (MS) S/D structures face difficulty in operating in the enhancement mode, as severe Fermi-level pinning (FLP) triggers extremely high off-state current ( ${I}_{ \mathrm{OFF}}$ ) and extremely low on-state current ( ${I}_{ \mathrm{ON}}$ ). The MIS S/D structure can solve these problems by mitigating FLP. In the simulation of an n-type Ge JLFET with the MIS S/D structure, ${I}_{ \mathrm{OFF}}$ of $9.42 \times 10^{-10}$ A/ $\mu \text{m}$ , ${I}_{ \mathrm{ON}}$ of $6.09 \times 10^{{-4}}$ A/ $\mu \text{m}$ , and subthreshold slope of 65.38 mV/dec are achieved. The performance of the device for different channel-doping concentrations and fin dimensions is also evaluated. Thus, an MIS S/D structure with a heavily doped interlayer can effectively strengthen the performances of n-type Ge JLFETs beyond the sub-7-nm technology node.

An analytical model for terahertz detection in cylindrical surrounding-gate MOSFETs

An analytical model for detection of terahertz radiation by plasma wave in cylindrical surrounding-gate (SRG) MOSFETs is presented. In comparison with traditional drain-current models, the rectification response of terahertz signal due to current self-mixing in conducting channel is considered by solving coupled plasma fluid equations using perturbation method. The resulted model is for the first time dipicting detector response in above threshold, near threshold and subthreshold regimes by a single expression valid for both resonant and nonresonant detection schemes. As no fitting parameters is adopted, the model is physical and predicative. Model validity has been extensively verified through numerically solving differential equations with a wide range of incident wave frequencies, channel doping concentrations, device working temperatures, SRG MOSFET geometry parameters as well as incident wave amplitudes. Model applicability to large input terahertz signal has also been discussed. The presented model is convenient for finding the optimum detector design from a multiparameter space. Its great universality will make it a candidate compact model for future terahertz integrated circuit simulation.

Linearity Distortion Analysis of Junctionless Quadruple Gate MOSFETs for Analog Applications

This paper examines a Junctionless quadruple gate (JLQG) MOSFET for analog and linearity distortion performance by numerically calculating transconductance and its higher order derivatives (gm1, gm2and gm3), VIP2, VIP3, IIP3 and IMD3. Influence of various physical device parameters: channel length, height (or width), gate oxide thickness, and channel doping concentration on the linearity distortion parameters are analyzed. From the numerical calculations it has been shown that the desirable characteristics for analog application at a given technology node are obtained for higher values of tSi, tox, and Nd. The present analysis also reveals the guidelines for the design of JLQG MOSFETs with least linearity distortion.

Mobility Fluctuation-Induced Low-Frequency Noise in Ultrascaled Ge Nanowire nMOSFETs With Near-Ballistic Transport

In this paper, we study the low-frequency noise in the Ge nanowire (NW) nMOSFETs with sub-100-nm channel length. The low-frequency noise with 1/ ${f}$ characteristics is proved to origin from the carriers’ mobility fluctuation. The dependences of low-frequency noise on NW geometry, channel length, equivalent oxide thickness (EOT), and channel doping concentration are examined by evaluating the Hooge parameters. It is shown that the low-frequency noise declines when the channel length of Ge NW nMOSFETs scales down, which is attributed to the electrons’ near ballistic transport. The electrons suffer more scatterings in the channels beneath the side walls of NWs or in the highly doped channels. The gate-oxide optimization is strongly demanded with the scaling down of EOT. Ultrascaled Ge NW nMOSFETs promise the enhancement of on-state performance and the suppression of low-frequency noise simultaneously.

Investigation of Channel Doping Concentration and Reverse Boron Penetration on P-Type Pi-Gate Poly-Si Junctionless Accumulation Mode FETs

In this paper, the influence of channel doping concentration and reverse boron penetration on p-type Pi-gate (PG) poly-Si junctionless accumulation mode (JAM) FETs has been experimentally investigated and discussed. Effective carrier concentration (Neff) and threshold voltage (VTH) are found to be sensitive to doping concentration. Moreover, the positive shift in VTH and the degradation in the subthreshold behavior for PG JAM FETs are observed after an additional source/drain (S/D) activation process. Using a low thermal-budget S/D activation process, PG JAM FETs with a suitable channel doping concentration can show excellent electrical characteristics: 1) steep subthreshold swing of 86 mV/dec.; 2) low average subthreshold swing (A.S.S.) of 96 mV/dec.; and 3) high ON/OFF current ratio (ION/IOFF) of 7.7 $\times $ 107 (ION at V G – VTH = −2 V and V D = −1 V).

Analysis and impact of process variability on performance of junctionless double gate VeSFET

This paper presents an in-depth analysis of junctionless double gate vertical slit FET (JLDG VeSFET) device under process variability. It has been observed that junctionless FETs (JLDG VeSFET) are significantly less sensitive to many process parameter variations due to their inherent device structure and geometric properties. Sensitivity analysis reveals that the slit width, oxide thickness, radius of the device, gate length and channel doping concentration imperceptibly affect the device performance of JLDG VeSFET in terms of variation in threshold voltage, on current, off current and subthreshold slope (Ssub) as compared to its junction based counterpart i.e. MOSFET, because various short channel effects are well controlled in this device. The maximum variation in off current for JLDG VeSFET due to variation in different devices parameters is 5.6% whereas this variation is 38.8% for the MOS junction based device. However, variation in doping concentration in the channel region displays a small deviation in the threshold voltage and on current characteristics of the MOSFET device as compared to JL DG VeSFET.

2-D Analytical Modeling of Surface Potential and Threshold Voltage for Vertical Super-Thin Body FET

In this paper, a 2-D analytical model for surface potential and threshold voltage of novel vertical super-thin body (VSTB) FET has been derived by solving 2-D Poisson equation. The analytical surface potential expression for gate-side surface and sidewall side surface has been modeled using parabolic surface potential approximation. The threshold voltage model for the VSTB FET has been derived by applying strong inversion criterion at the surface potential minimum value. The threshold voltage model for the VSTB FET has been analyzed by varying the body thickness, oxide thickness, and channel doping concentrations. The drain-induced barrier lowering and threshold voltage roll-off parameters are also extracted and analyzed for different body thicknesses. The models for surface potential and threshold voltage have been compared with the results obtained from the 2-D numerical device simulator and a very good agreement between the two has been observed.

Current-Voltage Model for Negative Capacitance Field-Effect Transistors

In this letter, a semi-analytical current–voltage model for a negative capacitance field-effect transistor (NCFET) with a ferroelectric material ( i.e. , BaTiO3) is proposed. Surface potential ( $\psi _{\mathrm {S}})$ in the channel region is determined first by solving the Landau–Khalatnikov (LK) equation numerically with Poisson’s equation. Then, the drain–current is achieved based on the current continuity equation using $\psi _{\mathrm {S}}$ determined earlier. In addition, by introducing a fitting potential for a given drain–voltage, threshold voltage shift can be captured, resulting in accurate surface potential and drain–current at different gate voltages. We have verified our model using the technology computer-aided design (TCAD)-MATLAB simulation, and our model exhibits an excellent agreement to the simulation results. In addition, the impacts of the ferroelectric thickness and channel doping concentration on the device performance and hysteresis window of NCFET are thoroughly explored.

Investigation on TG n-FinFET Parameters by Varying Channel Doping Concentration and Gate Length

In this paper, a 3D process of a nanometric n-channel fin field-effect transistor (FinFET) is discussed and the impact of variations of the fin parameter, the gate work function, and doping concentration on device characteristics are studied using the ATLAS Silvaco device simulator. Simulation results for various gate lengths are reported and analyzed. As the quantum effects are pronounced in nanoscale devices, we have included these effects in our study and simulation. We have then compared the achieved results to classical simulations to assess their performance limits. Finally, a comparison of our results with recently published data is presented to confirm our study.