Channel Doping Concentration Research Articles

Relation of Breakdown Voltage and Channel Doping Concentration of Sub-10 nm Double Gate MOSFET

Relation of Breakdown Voltage and Channel Doping Concentration of Sub-10 nm Double Gate MOSFET

RF stability performance of SOI junctionless FinFET and impact of process variation

In this paper we investigate the impact of process parameter variations such as temperature (T), channel doping concentration (ND), Fin height (Hfin) and Fin width (Wfin) on Radio Frequency (RF) stability performance of 20nm Silicon on Insulator Junctionless FinFET (SOI JLFinFET). The developed RF stability model provides relation between critical frequency (fk) and small signal parameters which can be optimized for improved stability. Results shows as temperature increases (27–200°C) cutoff frequency (fT) and maximum oscillation frequency (fmax) reduced by 12% and 8% respectively also stability factor (K) decreases by 20% at high frequency. Increasing ND, Hfin and Wfin increases fT and fmax but degrades stability performance. The result also provides optimized design guideline for operating SOI JLFinFET under RF range.

Study of novel junctionless Ge n-Tunneling Field-Effect Transistors with lightly doped drain (LDD) region

In this paper, a novel junctionless Ge n-Tunneling Field-Effect Transistors (TFET) structure is proposed. The simulation results show that Ion = 5.5 × 10−5A/μm is achieved. The junctionless device structure enhances Ion effectively and increases the region where significant BTBT occurs, comparing with the normal Ge-nTEFT. The impact of the lightly doped drain (LDD) region is investigated. A comparison of Ion and Ioff of the junctionless Ge n-TFET with different channel doping concentration ND and LDD doping concentration NLDD is studied. Ioff is reduced 1 order of magnitude with the optimized ND and NLDD are 1 × 1018cm−3 and 1 × 1017 cm−3, respectively. To reduce the gate induced drain leakage (GIDL) current, the impact of the sloped gate oxide structure is also studied. By employing the sloped gate oxide structure, the below 60 mV/decade subthreshold swing S = 46.2 mV/decade is achieved at Ion = 4.05 × 10−5A/μm and Ion/Ioff = 5.7 × 106.

Analytical model for random dopant fluctuation in double-gate MOSFET in the subthreshold region using macroscopic modeling method

An analytical model is proposed for the random dopant fluctuation (RDF) in a symmetric double-gate metal-oxidesemiconductor field-effect-transistor (DG MOSFET) in the subthreshold region. Unintended impurity dopants cannot be absolutely prevented during the device fabrication; hence, it is important to analytically model the fluctuations in the electrical characteristics caused by these impurity dopants. Therefore, a macroscopic modeling method is applied to represent the impurity dopants in DG MOSFETs. With this method, the two-dimensional (2D) Poisson equation is separated into a basic analytical DG MOSFET model with channel doping concentration NA and an impurity-dopant–related term with local doping concentration NRD confined in a specific rectangular area. To solve the second term, the manually solvable 2D Green’s function for DG MOSFETs is used. Through calculation of the channel potential (ϕ(x,y)), the variations in the drive current (IDS) and threshold voltage (Vth) are extracted from the analytical model. All results from the analytical model for an impurity dopant in a DG MOSFET are examined by comparisons with the commercially available 2D numerical simulation results, with respect to various oxide thicknesses (tox), channel lengths (L), and location of impurity dopants.

Method to predict length dependency of negative bias temperature instability degradation in p-MOSFETs

We propose a method to predict the length dependency of the magnitude of degradation caused by negative bias temperature instability (NBTI) stress applied to a p-MOSFET. Threshold voltage degradation ΔVth varied according to the drain bias Vd, during the measurement of drain current Id. The depletion length Ldep into the channel was calculated based on a particular Vd value and the channel doping concentration. Ldep was used to extract the channel edge region length Ledge, then the center channel region length Lcen was obtained by subtracting Ledge from the gate length Lgate. We proposed an equation that uses Ldep, Lcen, Ledge and degree of ΔVth variation to calculate ΔVth according to Lgate while the p-MOSFET is under NBTI stress. Equation estimates of ΔVth at different Lgate were similar to measurements.

Behavior of subthreshold conduction in junctionless transistors

In this work, the effect of high channel doping concentration and unique structure of junctionless transistors (JLTs) is investigated in the subthreshold conduction regime. Both experimental results and simulation work show that JLTs have reduced portion of the diffusion conduction and lower effective barrier height between source/drain and the silicon channel in subthreshold regime, compared to conventional inversion-mode (IM) transistors. Finally, it leads to a relatively large DIBL value in JLTs, owing to degraded gate controllability on channel region and strong drain bias effect. However, JLTs showed a better immunity against short channel effect in terms of degradation of the effective barrier height value.

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

ABSTRACTIn this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.

Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications

Ultra-low power logic applications at advanced CMOS technology nodes have been extensively investigated nowadays to increase packing density in Integrated Circuits at a lower cost. Junctionless (JL) transistors have emerged as promising alternatives to conventional MOSFETs because of their relatively easy fabrication steps and extreme scalability. We perform a detailed numerical study to evaluate the effects of channel doping concentration, dielectric constant of underlap spacers, source/drain resistance on logic performance of 20 nm gate length JL MOSFETs in terms of ON-current at a given OFF-current, subthreshold swing, gate capacitance and intrinsic delay for supply voltages ranging 0.4–0.75 V. In comparison with the reported experimental data for inversion-mode device, our optimized JL device exhibits enhancement of ION by 15.6%, reduction of drain-induced barrier lowering (DIBL) by 22.5% while preserving equally low SS of 61.5 mV/decade at channel length of 34 nm and supply voltage of 0.75 V.

The study of relation between variable retention time and channel implantation

In this paper, we investigate a Random Telegraph Signal (RTS) like junction leakage current causing a variable retention time (VRT) problem in Dynamic Random Access Memory (DRAM) cells. With sample devices which have different channel doping concentration, hold times of high leakage state and low leakage state are extracted in diverse storage node bias conditions, and their ratios are analyzed based on a simple equation. The hold time ratio of two states decreases with the increasing bias in high channel doping samples, while it increases in both regular channel doping samples and low channel doping samples.

비대칭 이중게이트 MOSFET에 대한 DIBL의 채널도핑농도 의존성

비대칭 이중게이트 MOSFET에 대한 DIBL의 채널도핑농도 의존성

Design optimization of vertical nanowire tunneling field-effect transistor based on AlGaSb/InGaAs heterojunction layer

This paper presents the electrical characteristics of vertical nanowire-type tunneling field-effect transistors (VNW TFETs) based on the AlGaSb/InGaAs heterojunction for low-power, high-speed applications. The proposed devices have a very steep junction, based on broken band alignment between the AlGaSb and InGaAs layers. The extremely thin tunneling barrier increases the tunneling probability between the AlGaSb source region and the InGaAs channel region. For this reason, the broken band based on the AlGaSb/InGaAs heterostructure enhances the on-state current (Ion) of the TFETs. To optimize the electrical performance of the proposed device, design optimization using technology computer-aided design (TCAD) simulations is performed. The design variables are gate length, doping concentrations, and the nanowire radius. The optimized device has a gate length of 30 nm, channel and drain doping concentrations of 1018 cm−3, and a radius of 10 nm. Results confirm that the optimized TFET has a subthreshold swing (S) of 27.8 mV/dec and an Ion value of 2.57 mA/μm.

Analytical model for an asymmetric double-gate MOSFET with gate-oxide thickness and flat-band voltage variations in the subthreshold region

This paper proposes an analytical model for an asymmetric double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) with varying gate-oxide thickness (tox) and flat-band voltage (Vfb) in the subthreshold region. Since such variations cannot be completely avoided, the modeling of their behaviors is essential. The analytical model is developed by solving a 2D Poisson equation with a varying channel doping concentration (NA). To solve the 2D Poisson equation of the asymmetric DG MOSFET, a perturbation method is used to separate the solution of the channel potential into basic and perturbed terms. Since the basic terms can be regarded as the equations derived from a general symmetric doped DG MOSFET, the conventional analytical model is adopted. In addition, a solution related to the perturbed terms for the asymmetric structures is obtained using Fourier series. Based on the obtained channel potential, the electrical characteristics of the drive current (IDS) are expressed in the analytical model. The prediction of the electrical characteristics by the analytical model shows excellent agreement when compared with commercially available 2D numerical device simulation results with respect to not only tox and Vfb variations but also channel length and NA variations.

Modeling Statistical Dopant Fluctuations Effect on Threshold Voltage of Scaled JFET Devices

This paper presents a simple mathematical expression to model the effect of statistical dopant fluctuations on threshold voltage ( $V_{th}$ ) of junction field-effect transistors (JFETs). The random discrete doping (RDD) in the active device area is used to derive an analytical model to compute the standard deviation, $\sigma V_{th,RDD}$ of the $V_{th}$ -distribution for any arbitrary channel doping profiles. The model shows that the $V_{th}$ -variability in JFETs depends on the active device area, channel doping concentration, and the depth of the channel depletion region of the gate/channel $pn$ -junction. The model is applied to compute $\sigma V_{th,RDD}$ for symmetric and asymmetric source/drain double-gate n-channel JFETs. The simulation results show that the model can be used for predicting $V_{th}$ -variability in JFETs.

A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric

A 2-D analytical threshold-voltage model for ultra-thin-body MOSFET with buried insulator and high-k gate dielectric is established by solving the 2-D Poisson's equation for the gate-dielectric, channel and buried-insulator regions. The validity of the model is confirmed by comparing with experimental data and other models. Using the model, the influences of gate-dielectric permittivity, buried-insulator permittivity, channel thickness, buried-insulator thickness and channel doping concentration on threshold behaviors are investigated. It is found that the threshold behaviors can be improved by using buried insulator with low permittivity, thin channel and high channel doping concentration. However, the threshold performance would be degraded when high-k gate dielectric is used due to enhanced fringing-field effect.

SEB Hardened Power MOSFETs With High-K Dielectrics

Simulations of the SEB hardness of power MOSFETs are carried out with an experimentally calibrated structure. The effects of incorporating high permittivity gate dielectric layers and increasing channel doping concentration are investigated. The simulation results indicate that high-k dielectrics and high channel doping are promising methods to achieve SEB-hardened power MOSFETs. This offers a potential path to power MOSFETs that are resistant to SEB with thinner, more radiation-tolerant gate dielectrics.

Leakage current of germanium-on-insulator-based junctionless nanowire transistors

Junctionless nanowire transistors (JNTs) have been fabricated on ultra-thin-body germanium-on-insulator (GOI) substrates using a simple Si-compatible top-down process. These JNTs, which have gate lengths and widths that are both less than 100 nm, exhibit good electrical characteristics (Ion/Ioff ratio of ∼105 at Vd = −1 V). The effects of the back gate voltage, temperature, the device dimensions, and the channel doping concentration on the leakage currents of the fabricated devices were experimentally analyzed in detail. The results indicate that the leakage current is mainly affected by the gate tunneling current, the Shockley-Read-Hall generation current, the band-to-band tunneling current and the trap-assisted tunneling current. Design guidelines were then proposed to reduce the leakage currents of GOI-based JNTs.

Analysis of Graphene Tunnel Field-Effect Transistors for Analog/RF Applications

The recent findings of quasi-saturation and negative differential resistance in graphene FET have motivated the researchers to improve the current saturation behavior. We suggest that tunnel FET (TFET) with graphene can be a potential candidate for better current saturation. In this regard, the electronic transport in zero bandgap graphene TFET (T-GFET) is studied through the self-consistent solution of Schrödinger equation within ballistic nonequilibrium Green's function formalism, and 2-D Poisson's equation. We show that the appropriate drain overlap, and channel and drain doping concentrations in T-GFET can significantly suppress the channel to drain tunneling current and, consequently, enhance the current saturation. Despite T-GFET's lower ON-current, it shows moderately higher intrinsic gain, compared with conventional graphene FET (C-GFET). Furthermore, the channel length dependence of intrinsic gain and cutoff frequency for T-GFET is investigated and compared with C-GFET.

10 nm 이하 비대칭 DGMOSFET의 채널도핑농도에 따른 터널링 전류

This paper analyzes the ratio of tunneling current for channel doping concentration of sub-10 nm asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current in subthreshold region increases in the region of channel length of 10 nm below. Even though asymmetric DGMOSFET is developed to reduce short channel effects, the increase of tunneling current in sub-10 nm is inevitable. As the ratio of tunneling current in off current according to channel doping concentration is calculated in this study, the influence of tunneling current to occur in short channel is investigated. To obtain off current to consist of thermionic emission and tunneling current, the analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for channel doping concentration in sub-10 nm asymmetric DGMOSFET, specially with parameters of channel length, channel thickness, and top/bottom gate oxide thickness and voltage.

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson's equation using "variable separation technique". The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.

Design and characterization of electrically self-isolated GaN-on-Si junctionless fin-shaped-channel field-effect transistor with higher cost-effectiveness for low-power applications

A GaN-on-Si junctionless FET with a feasible structure is suggested and simulated. A silicon-on-insulator channel is replaced by a GaN-on-Si channel in the proposed device. The GaN-on-Si heterostructure forms an electrically self-isolated channel owing to its large band offset. Two- and three-dimensional (2D and 3D) device simulations were cooperatively performed to optimize the device in terms of gate length, channel thickness, channel doping concentration, and substrate concentration, targeting low-power applications.