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Abstract
A GaN-on-Si junctionless FET with a feasible structure is suggested and simulated. A silicon-on-insulator channel is replaced by a GaN-on-Si channel in the proposed device. The GaN-on-Si heterostructure forms an electrically self-isolated channel owing to its large band offset. Two- and three-dimensional (2D and 3D) device simulations were cooperatively performed to optimize the device in terms of gate length, channel thickness, channel doping concentration, and substrate concentration, targeting low-power applications.
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