Junctionless-FET fabrication using NH<inf>4</inf> OH solution wet etching for silicon channel thinning

Abstract

Junctionless-FET (JL-FET) devices were fabricated on SOI substrate using NH$_{\mathbf{4}}$ OH as means to thin the channel substrate. The devices gate dielectric was silicon oxynitride grown using O$_{\mathbf{2}} {/\mathbf{N}}_{\mathbf{2}}$ ECR (Electron-Cyclotron-Resonance) plasma, and its gate metal was TiN, which was defined by lift-off and deposited using reactive sputtering. The electrical contacts were fabricated with sputtered aluminum, defined by lift-off and sintered in conventional furnace. The final channel thickness was 63 nm, measured using SEM (Scanning Electron Microscopy) imaging. The channel dopant concentration was estimated at approximately 10$^{\mathbf{17}}\textbf{ atoms/cm}^{\mathbf{3}}$ based on the pseudo-MOS electrical measurements. JL-FET electrical measurements indicated the transistor behavior, despite the negative threshold voltage and the electrical contacts with high resistances. These results are as expected due to the measured channel thickness (of 63 nm) and the estimated channel dopant concentration (10$^{\mathbf{17}}\textbf{atoms/cm}^{\mathbf{3}}$). Furthermore, all Pseudo-MOS and JL-FET device measurements showed that the thinned channel is working very well, and that the silicon etching in NH$_{\mathbf{4}}$ OH solution is a viable technique to fabricate JL-FET devices.