Random dopant fluctuations impact reduction in 7 nm bulk-FinFET by substrate engineering

Abstract

Currently, fin-field-effect-transistors (FinFETs) are used at 7 nm technology node, in order to avoid parasitic leakage channel under the controlled channel punch-through-stopper (PTS) doping is used with the bulk Silicon substrate (PTS-Si substrate). The dopants from PTS doping enters into the channel during the annealing process and increases channel doping level. The increased doping concentration in channel causes undesirable effects such as reduction in channel mobility and increase in random-dopant-fluctuations (RDFs). Using a silicon-on-insulator (SOI) substrate is a costlier solution, this work presents super-steep-retrograde-silicon (SSR-Si) substrate as a better solution for this problem. In this work, the SSR-Si substrate is achieved by placing lightly doped 10 nm thick SSR-buffer layer (silicon) on top of PTS-Si substrate. This SSR-buffer layer captures dopants intruding from PTS doping into channel thereby achieves SSR doping profile in the channel. The results show SSR-Si substrate reduces the RDF induced threshold variations by 50%, it also provides better DC and RF/analogue metrics than PTS-Si substrate and comparable with SOI substrate.