DLTS Technique Research Articles

Transient Scanning Electron Beam Annealing Methods Used to Study Diffusion and Defects in Implanted Silicon

AbstractRapid thermal annealing of arsenic and boron difluoride implants, such as those used for source/drain regions in CMOS, has been carried out using a scanning electron beam annealer, as part of a study of transient diffusion effects. Three types of e-beam anneal have been performed, with peak temperatures in the range 900-1200°C; the normal isothermal e-beam anneals, together with sub-second fast anneals and ‘dual-pulse’ anneals, in which the sample undergoes an isothermal pre-anneal followed by rapid heating to the required anneal temperature in less than O.5s.The diffusion occuring during these anneal cycles has been modelled using SPS−1D, an implant and diffusion modelling program developed by one of the authors. This has been modified to incorporate simulated temperature vs. time cycles for the anneals. Results are presented applying the usual equilibrium clustering model, a transient point-defect enhancement to the diffusivity proposed recently by Fair and a new dynamic clustering model for arsenic. Good agreement with SIMS measurements is obtained using the dynamic clustering model, without recourse to a transient defect model.Defects remaining in diodes fabricated with the forementioned implants after these anneal cycles have been studied using DLTS techniques. Trap densities for the three types of e-beam anneal are comparable to those for furnace annealed diodes, as are the reverse leakage currents measured (typically 2–5nA for a 0.85mm2 diode at -5V).

A Model for the Application of Dlts on Normally-on Hemt Structures

ABSTRACTThis paper presents an analytical model for the application of capacitance DLTS on the normally-on HEMT structure. Based on the charge conservation law, the DLTS signal is derived by taking into account both the Schottky gate and the heterojunction depletion layer capacitances. It is shown that the anomalous features observed by using the conventional DLTS technique on a HEMT structure can be reasonably explained with this model. Some results obtained by simulation of typical measurements are presented, which confirm our conclusions.

Dependence of deep-level parameters in ion-implanted GaAs MESFET's on material preparation

A detailed study of the characteristics and origin of deep level traps in device-quality Si-implanted GaAs and in MESFET's has been made using an ultrasensitive optical DLTS technique. Efforts were made to elucidate the conditions which reduce or enhance trap concentrations. The effects of etching and long-term baking of substrates prior to implantation and prolonged annealing after implantation were investigated. These measurements were complemented by low-temperature photoluminescence measurements to establish the corresponding variation in the quality of the material. Several electron and hole traps were commonly observed, ranging in activation energy from 0.21 to 1.1 eV. It is believed that some of these centers are distributed in energy. Among others, two hole traps with activation energies of 0.43 and 0.72 eV and a 0.57-eV electron trap are dominantly present. The first is believed to be due to Cu, the second is probably related to a native defect and the electron trap seems to originate from lattice damage. The other centers are possibly complexes related to lattice damage and vacancies. Under certain conditions, changes in trap densities could be correlated with corresponding changes in some device parameters.

A DLTS technique for surface state capture cross-section measurement of MOS diodes

A modified DLTS technique is proposed for the direct measurement of capture cross-section of MOS surface states. The nature of temperature and energy dependence σ n is inferred from data analysis. Temperature dependence of σ n is shown to be consistent with the observed DLTS line shapes.

A DLTS technique for surface state capture cross-section measurement of MOS diodes

A modified DLTS technique is proposed for the direct measurement of capture cross-section of MOS surface states. The nature of temperature and energy dependence σ n is inferred from data analysis. Temperature dependence of σ n is shown to be consistent with the observed DLTS line shapes.

DIRECT OBSERVATION OF INTERFACE TRAPS IN OMVPE-GROWN SELECTIVELY AlGaAs/GaAs HETEROSTRUCTURE USING MODIFIED DLTS

AbstractBy using a DLTS technique, we measured the drain current transient from a gate bias pulse for a HEMT. Two negative peaks and one positive peak were observed. From the analysis of the spectra, we found that the positive peak was due to the interface trap. The density of the interface trap was determined from a DLTS fitting procedure. The effect of the interface traps on the electrical properties of the heterostructure are discussed.

Deep Level Spectra of Ion-Implantation Defects and Slip Dislocations Introduced by CO2 Laser

ABSTRACTThe CW CO2 laser annealing is an effective method for removing deep level defects induced by ion-implantation. The available laser density range is 350˜600 W/cm2, which is consistent with that needed to fully activate implanted impurities. At high power density (>600W/cm2 ) slip dislocations can be induced. The energy spectra of dislocations were measured with DLTS technique. One peak at Ev + 0.33eV in p-Si and two at peaks at Ec −0.37eV and Ec −0.50eV in n-Si have been found. These peaks are stable during thermal annealing at high temperature. But they can be passivated with hydrogen plasma annealing and reactivated by subsequent thermal annealing in vacuum. The dislocation core is reconstructed.

Characterization of the grown-in defects in Zn-doped InP

Studies of the effect of low temperature thermal annealing (170 °C) and laser annealing on grown-in defects in LEC grown Zn-doped InP have been made using the DLTS technique. One hole trap with energy of E v+∅.52 eV and density of 1.8×10∅ 15 cm −3 was observed in these InP samples. The potential well for this hole trap was determined by comparing the calculated field dependent emission rates with the field enhanced emission rate data obtained from the DLTS measurements. The results show that the potential well for this hole trap may be due to either a Dirac well or a square well, and hence the physical origin for this hole trap is attributed to either a phosphorus vacancy or a phosphorus interstitial related defect.

Direct measurement of interface state electron capture cross-section in MOS system by DLTS technique

The interface states at the $Si-Si0_2$ interface are characterized by their distribution in the energy band gap and capture cross-sections for electrons and holes.

Annealing behaviour of gamma-ray-induced electron traps in LEC n -InP

The annealing behaviour of a gamma-ray-induced dominant electron trap (Ec − 0.79 eV) in LEC undoped n-InP is studied by means of the DLTS technique. The isothermal annealing experiment shows it is a first-order process with an activation energy of 0.98 eV; this value is much smaller than those found in room-temperature-irradiated n-GaAs.

Characterization of the potential well of a deep-level defect using field dependence of the thermal carrier emission rate

The electric field enhanced thermal emission rate was measured for the E c -0.35 eV level of GaAs using a new reverse-bias pulsed DLTS technique. It is shown that the observed field and its temperature dependencies are probably the result of the Poole-Frenkel emission from a polarization potential well. From this study and with other annealing and the capture cross-section data, it is concluded that the defect is probably of a neutral-impurity type.

Characterization of electron traps in ion-implanted GaAs MESFET's on undoped and Cr-doped LEC semi-insulating substrates

This paper presents the results of characterization of deep levels in ion-implanted layers on semi-insulating LEC GaAs substrates, using MESFET channel current DLTS and transient resistance techniques. Test devices on undoped substrates show six electron traps with activation energies ranging from 0.15 to 0.85 eV, and devices on lightly and heavily Cr-doped substrates show five-and two-electron traps, respectively. The well-known EL2 level is the dominant level in undoped and lightly Cr-doped material, and there are two-electron traps (0.22 and 0.85 eV) that exist only in undoped material, and with the addition of Cr they are suppressed and a new level at 0.64 eV emerges instead. A deep level at 0.53 eV was observed in all samples and whether this arises due to implantation and annealing or it is a characteristic of the LEC material is as yet unknown.

Characterization of surface states in MOS capacitors by a modified DLTS technique

A modified DLTS technique for characterization of surface states in MOS structure is proposed. It involves scanning the bias while applying small filling pulses at constant temperature. The surface states behave as discrete levels when the pulses are small. Results on a CuSiO2pSi tunnel diode are presented as example. Eine modifizierte DLTS-Technik zur Charakterisierung der Oberflachenzustande in MOS-Strukturen wird vorgeschlagen, die in einer Anderung (scanning) der Vorspannung besteht, wahrend kleine Fullimpulse bei konstanter Temperatur angelegt werden. Die Oberflachenzustande zeigen sich als diskrete Niveaus, wenn die Impulse klein sind. Als Beispiel werden die Ergebnisse an einer CuSiO2–p-Si-Tunneldiode mitgeteilt.

The effects of deep levels in GaAs MESFETs

The electrical characteristics of a GaAs MESFET are shown to be variously affected by deep levels, depending on their location in the gap and where they are in the device. An appropriate variation of the DLTS technique can be used to characterize deep levels in a MESFET. Measurements performed at emission time constants down to 0.6 ns have permitted a quantitative study of microwave noise due to electron traps in the channel. A spurious backgating effect in GaAs integrated circuits is due to hole traps on the substrate side of the active layer-substrate interface. The free surface of GaAs MESFETs is usually depleted due to the presence of surface states. Their charge state can be modified by lateral carrier transport on the GaAs surface, which affects the device electrical performances.

Influence of interface states on field effect and capacitance-voltage characteristics of metal/oxide/a-Si:H structures

Separate determination of the electronic density of states in bulk a-Si:H and at the oxide/a-Si:H interface of a MOS structure have been made by combining the field effect technique with the capacitance-voltage method. It is found that electronic states existing at the oxide/a-Si:H interface cause no serious errors in the determination of the bulk gap-state density. The discrepancy in the measured gap-state density between the present method and the DLTS or ICTS techniques does not arise from the presence of surface states, but from differences in the electronic properties of a-Si:H.

Interpretation of profiles obtained by C( V) technique in presence of deep traps: Application to proton irradiated GaAs samples

In the present paper, we attempt to give a mathematical form to the results of the “profiles” obtained by the C( V) method. The theory is performed in the case of a donor or acceptor like trap. The results are applied to a uniform trap profile (case of electron irradiation) and a gaussian trap profile (case of ion irradiation). The temperature variation, the trap localization in the gap and the effect of the Fermi level, which gives the spatial separation between the empty and full defect, has been taken into account. The variation of the crossing point between the Fermi level and the trap level with the voltage has been evaluated in some particular cases. The theoretical results are applied to experiments on proton irradiated n type (2.10 15/cm 3) epitaxial VPE GaAs. In the irradiated samples, two dominant defects labeled E 2 ( E c − 0.22 eV) and E 3 ( E c − 0.33 eV) have been identified by DLTS technique. A good fit of experimental C( V) “profiles” by the model exposed in this paper is obtained. This result leads us to confirm E 2 ( E c - 0.22 eV) and E 3 ( E c - 0.33 eV) as acceptor like traps in n type GaAs.

Defect States in n-Type Germanium Irradiated with 1.5 MeV Electrons

The defect levels produced in antimony- or arsenic-doped germanium by irradiation with 1.5 MeV electrons and the annealing behaviour of these materials were studied by the DLTS technique. The position of the levels formed by radiation-induced defects was determined and the dependence of the level position on the species and concentration of the impurity atoms are reported. The defects associated with the Ec–0.40 eV level and the Ec–0.23 eV level are thought to be formed by the association of antimony atoms with unidentified defects. From the results of annealing under injection, the defects associated with the Ec–0.23 eV level are considered to be annealed by a recombination-enhanced mechanism.

Properties of the gold related acceptor level in silicon

The apparent thermal activation energy of 0.56 eV and the electron thermal capture cross section of 2.0 × 10−16 cm2 are measured for the gold related acceptor level in p+ nn+ silicon diodes by isothermal current transient and DLTS techniques. Using the emission and capture rate data and a degeneracy ratio of 2, the energy separation of the trap level from the conduction band is calculated and found to have the same temperature dependence as the band gap indicating that the acceptor level is pinned with respect to the valence band a t Ev + 0.637 eV. Fur das mit Gold verknupfte Akzeptorniveau in p+ nn+-Siliziumdioden wird eine scheinbare thermische Aktivierungsenergie von 0,56 eV und ein Einfangquerschnitt von 2,0 × 10−16 cm2 fur thermische Elektronen gemessen; es werden dabei das Verfahren des isothermisohen Einschwingstromes und das DLTS-Verfahren angewandt. Der Energieabstand des Einfangniveaus vom Leitungsband wird mit Hilfe der Emissions- und Einfanggeschwindigkeitsdaten und eines Entartungsverhliltnisses von 2 berechnet. Es zeigt sich, das dieser Energieabstand dieselbe Temperaturabhangigkeit hat wie die Bandlucke. Das bedeutet, das das Akzeptorniveau bezogen auf das Valenzband bei Ev + 0,637 eV liegt.

Anodic Al2O3/InP MIS interface and its application to enhancement-MISFET's on semi-insulating substrates

A simple process to grow anodically high-quality Al2O3, films on InP substrates with good adhesion, is described. The AGW electrolyte is employed. The resultant oxide is uniform and possesses resistivity values in excess of 1015 Ωcm with a breakdown field strength of about 2–3 × 106 V/cm. Properties of anodic Al2O3/InP interfaces arc clarified by quasi-static capacitance-voltage and dynamic DLTS and photo-ionization techniques. The results are. consistent, and indicate that the distribution of interface states in U-shaped in the upper half of the bandgap, making a sharp contrast to the case of GaAs MIS systems. The anodic Al2O3n-InP MIS interface exhibits extremely small frequency dispersion on the accumulation side, and the surface Fermi level can be brought up as close as 0[sdot]05 eV to the conduction band edge. Using the present Al2O3, films, n-channel enhancement MISFET's were successfully constructed directly on Fe-doped semi-insulating substrates with the channel mobility of 300 cm2/Vs.

Quenched-in deep levels in boron-doped silicon

The DLTS technique was used to study quenched-in deep traps in boron doped silicon crystals, heated at temperatures in the range 700–900°C prior to quenching. The results vary with temperature, demonstrating that the exact temperature up to which the samples are heated prior to quenching plays a determining role on the number of different traps intorduced and their positions in the energy gap, which is often overlooked in the literature.