Direct Digital Frequency Synthesizer Research Articles

The Design and Implementation of High Precision Three-Phase Sine-Wave Signal Generator

A design and implementation method of high precision three-phase sine-wave signal generator is proposed based on MCU and FPGA. For the traditional design method, direct analog synthesis method and phase locked loop (PLL) technology are used to design the signal generator. So the function, the precision and other aspects are inadequate. Aiming to the problem, a signal generator is designed based on direct digital frequency synthesis (DDS) technology. The MCU is used to control the peripheral devices and the frequency and phase control word can be obtained. The DDS module is achieved by EP4CE6E22C8 and the waveform lookup table addresses are outputted. The digital three-phase sine-wave data can be read from the lookup table. Through the three-way D/A converter and the amplifier circuit, the digital signal is converted to analog signal and the three-phase sinusoidal wave is outputted. The precision can be improved by increasing the sampling points, phase accumulator bits and D/A bits, and then, high precision three-phase sine-signal can be obtained and the adjustable frequency precision is 0.001.

Optimization of the Quantized Coefficients for DDFS Utilizing Polynomial Interpolation Methods

In this brief, a novel method to find the optimized quantized coefficients for direct digital frequency synthesizers (DDFSs) based on polynomial interpolation methods is introduced. First, a new method is introduced to find the spurious-free dynamic-range upperbound for DDFSs with a polynomial interpolation method, utilizing the discrete Fourier transform and the Chebyshev minimax problem. This method can be modified to obtain quantized coefficients by employing mixed-integer linear programming. In this problem, the polynomial coefficients are presented in a positive sum of powers of two (SPT) and unsigned integer forms. The proposed method is used to design the linear interpolation-based DDFSs with nonuniform segmentations. The VLSI realizations of the designs with nonuniform segmentations are provided, where it is shown that they have a smaller silicon area and higher clock frequencies compared with the state-of-the-art designs reported in literature.

A 2.5-GHz Direct Digital Frequency Synthesizer with spurious noise cancellation

A 2.5 GHz Direct Digital Frequency Synthesizer (DDS) with spurious noise cancellation is presented. Seven auxiliary DDSs have been used as spur cancellers which can generate opposition signal to counteract the spurs in DDS’s output spectrum. Principle of spur cancellation and its implementation scheme is discussed. Key steps of spur cancellation procedure are also described. This DDS is implemented in a 0.18 µm CMOS technology, occupies 4.6 mm × 4.2 mm including bond pads. Measured performance is SFDR > 58 dB for output signal frequencies up to 1 GHz, more than 20 dB’s improvement is achieved comparing to its intrinsic SFDR performance.

Hardware implementation of 32-bit high-speed direct digital frequency synthesizer.

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

A ROM-less direct digital frequency synthesizer based on hybrid polynomial approximation.

In this paper, a novel design approach for a phase to sinusoid amplitude converter (PSAC) has been investigated. Two segments have been used to approximate the first sine quadrant. A first linear segment is used to fit the region near the zero point, while a second fourth-order parabolic segment is used to approximate the rest of the sine curve. The phase sample, where the polynomial changed, was chosen in such a way as to achieve the maximum spurious free dynamic range (SFDR). The invented direct digital frequency synthesizer (DDFS) has been encoded in VHDL and post simulation was carried out. The synthesized architecture exhibits a promising result of 90 dBc SFDR. The targeted structure is expected to show advantages for perceptible reduction of hardware resources and power consumption as well as high clock speeds.

The used of operations without carry in high-speed computing frequency synthesizers

The use of new mathematical approaches to constructing phase accumulators of direct digital frequency synthesizers without the problem of delay of carry signal distribution from one category to another was proposed in this paper. The causes of delay of synthesized signals and deterioration of their spectral characteristics in direct digital computing frequency synthesizers were considered. It was found that one of the major causes is the delay of carry signals in the phase accumulator of the synthesizer, based on the accumulating adder. It was shown that, with the increase of the synthesizer capacity, the duration of delays of carry signals starts playing the key role and influences directly such synthesizer parameter as the maximum operating frequency. In the paper, it was determined that one of limiting factors in terms of the maximum speed and qualitative spectral structure of digital frequency synthesizers is the speed of certain arithmetical summing operations in the core of digital synthesizer. The possibility of applying operations in the Galois field for improving the synthesizer speed was considered. Mathematical operations of adding and subtracting number pairs without the carry were developed. The same approach can be used for performing operations with greater capacity. The proposed mathematical tool will allow constructing the digital computing synthesizer without the problem of delay of carry signals by some complication of the phase accumulator structure.

FPGA-Based Implementation of a New Phase-to-Sine Amplitude Conversion Architecture

The classical structure of linear interpolation-based phase-to-sine mapper (PSM) consists of at least two ROMs for polynomial coefficient storage. Other architectures may include extra ROM for storing residual errors. However, ROMs dissipate high power and occupy a significant amount of the die area. This study presents a new technique that eliminates the ROM by including the computation of segment initial coefficients in the hardware. Therefore, it becomes possible to trim down noticeable hardware resources. The proposed direct digital frequency synthesizer (DDFS) architecture has been encoded in VHDL and synthesized with Quartus II software. Post simulation results show that the proposed design is capable of achieving the theoretical spurious-free dynamic range (SFDR) upper bound when optimal polynomial coefficients are considered. For 32 piecewise linear segments, the SFDR of the synthesized sinusoid is 84.15 dBc. A ROM compression ratio of 597.3:1 was also achieved. The performance of the DDFS is compared with previously presented DDFS techniques and the results show that the proposed design has advantages of high ROM compression ratio and low hardware complexity. DOI: http://dx.doi.org/10.5755/j01.eee.19.10.5905

Implementation of a 32-bit High Speed Phase Accumulator for Direct Digital Frequency Synthesizer

Implementation of a 32-bit High Speed Phase Accumulator for Direct Digital Frequency Synthesizer

Low‐power pipelined phase accumulator with sequential clock gating for DDFSs

A pipelined phase accumulator (PACC) for direct digital frequency synthesisers (DDFSs) is presented. A highly pipelined structure is inevitable in a PACC design to achieve high-speed performance, which causes a large number of pre-skewing flip-flops (F/Fs) and leads clock signals to be a large source of power dissipation. Since the input data do not change every single cycle, clock gating can save power by decreasing the number of unnecessary clock switching in the pre-skewing F/Fs. Sequential clock gating for pipelined PACCs is proposed. Compared with the conventional pipelined PACCs with and without clock gating, the proposed scheme reduces power dissipation by up to 55.4 and 77.2%, respectively, for the 32-bit 8-pipeline-stage PACCs.

A 4 GHz 32 bit direct digital frequency synthesizer based on a novel architecture

This paper presents a novel direct digital frequency synthesizer (DDFS) architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method, which has the advantages of high speed, low power and low hardware resources. By subdividing the sinusoid into a collection of phase segments, the same initial value of each segment is realized by a nonlinear DAC. The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method. Then, the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment. Meanwhile, the fine ROM stores the differences between the line values and the initial value of each line. A ROM compression ratio of 32 can be achieved in the case of 11 bit phase and 9 bit amplitude. Based on the above method, a prototype chip was fabricated using 1.4 μm GaAs HBT technology. The measurement shows an average spurious-free dynamic range (SFDR) of 45 dBc, with the worst SFDR only 40.07 dBc at a 4.0 GHz clock. The chip area is 4.6 × 3.7 mm2 and it consumes 7 W from a −4.9 V power supply.

Frequency Conversion Type Ultrasonic Power Based on DSP Control Technology Research

The introduction of the direct digital frequency synthesis (DDS) technology in the field of communication is against the traditional ultrasonic machining power supply which does not have the multi-frequency tracking shortcomings to build a frequency conversion type ultrasonic power. Frequency conversion type ultrasonic power supply is based on DSP embedded system and adopts direct digital frequency synthesis (DDS) technology combined with a software phase locked frequency of composite frequency tracking scheme to realize automatic search transducer resonance frequency and frequency automatic tracking function which can response the different characteristics of the transducer dynamical; With the use of phase shift control power-principle to realize the output power regulating function when the frequency changes and reduce the switching power loss; It provides an important reference for the design of new frequency conversion type ultrasonic power.

Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA

The Direct Digital Frequency Synthesizer (DDFS) is a critical component routinely implemented in communication or signal processing systems.The recent literature proposes various DDFS implementation techniques that, implemented by using state of the art Application Specific Integrated Circuits (ASIC) technologies, provide ever improving performances in terms of speed, power dissipation and silicon area occupation.The performance trend provided by the advanced designs that target ASIC technologies is not guaranteed to remain the same when the target technology is a commercially available Field Programmable Gate Array (FPGA) device.This paper presents the FPGA implementation of the best performing DDFS architectures proposed to date. DDFS performance trends are compared with the ASIC implementations. Further, the state of the art DDFS circuits are modified in order to better suit the FPGA technology and compared against the DDFS implementations obtained using Intellectual Properties (IPs) included in the design suites of the FPGA manufacturers. The comparison is conducted considering as implementation target various (both low end, middle range, and high end) FPGA devices produced by different vendors. Considered performance parameters are the maximum working frequency, the dynamic power dissipation, the logic resource occupation, and the precision of the DDFS measured in terms of Spurious Free Dynamic Range (SFDR).The analysis shows that when dealing with FPGA implementations, it is important that the implemented architectures adapt to the internal logic resources of the FPGA. For low SFDR values the best performing architectures are the straightforward ROM based ones that optimally fit in the very fast Block RAM of the FPGA. When the required SFDR increases more advanced architectures are required. The optimal architectures also depend on the design choice of privileging high working frequency or reduced power dissipation.

Study on Ultrasonic Generator for Ultrasonically Assisted Machining

Ultrasonic vibration cutting can be widely used in lathe, planer, milling machine, grinding machine, thread processing and gear processing, etc. Ultrasonic vibration cutting system is composed mainly of ultrasonic generator, ultrasonic transducer, luffing rod, cutting tool, etc. Here, ultrasonic generator is the most important. The stand or fall of signal, which is produced by ultrasonic generator, has direct influence on anticipated effect and ability of ultrasonic machining. In order to generate a signal, which can be suitable for ultrasonic machining, ultrasonic vibration cutting system is studied, and ultrasonic signal generator based on direct digital frequency synthesis (DDS) is designed and conducted a cutting test with this ultrasonic machining system. The results show that the signal generator, which is made up by DDS technology, can generate the signal with stability, reliability and greater flexibility, and can be fully applicable to the ultrasonic machining.

The Design and Simulation of DDS Based on Multisim and C51

In order to facilitate intuitive and understanding of the frequency synthesizer technology, research on direct digital frequency synthesizer by the phase accumulator , waveform storage ROM, the D/ Aconverter and low-pass filter modules .Multisim provides powerful virtual electronic platform, realize DDS synthetic sine wave design and circuit simulation by C51 MCU control center, while providing key code. By adjustingthe reference clock frequency fc, or to adjust the frequency control word K, can be clearly seen of the frequency of the synthesized sine wave will be changed.

Based on FPGA Design and Simulation of Function Signal Generator

Based on direct digital frequency synthesizer ( DDS ) of the working principle, designfunction signal generator based on FPGA chip as the core, the application of Verilog language andQuartus II provided by software schematic design function, completed a system circuit design, using Modelsim on the circuit in the simulation, the simulation results are analyzed, the validationof the design method for the reliability and feasibility.

FPGA Implementation of Direct Digital Frequency Synthesizer

Direct digital frequency synthesizer (referred to as DDS) is a kind of complete digital frequency synthesizer. In this article the principle of DDS were introduced. Set the design index of distortion and resolution, and design parameters of DDS in accordance with the index. DDS design describes by Verilog HDL, implement controlling four parameters of the waveform, frequency, phase, amplitude. Using FPGA and Quartus II/Nios IIwhich is Altera EDA software, realize DDS and its peripheral input / output and DA platform. The final direct to DDS simulation results and the overall DDS platform oscilloscope experimental data, verify the correctness of the design of DDS with the two data.

A 10-Bit 2-GS/s DAC-DDFS-IQ-Controller Baseband Enabling a Self-Healing 60-GHz Radio-on-Chip

A 10-bit 2-GS/s mixed-signal baseband (BB) circuit, which enables a self-healing 60-GHz 4-Gb/s radio-on-chip implemented in a 65-nm complementary metal-oxide semiconductor, is described. The BB circuit autonomously senses and optimizes transmitter (TX) P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> , OIM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , and image suppression, reducing the yield loss because of process variations. On-chip test tones are generated using a 10-bit 2-GS/s current-steering digital-to-analog converter (DAC) and direct digital frequency synthesizer (DDFS). Using the generated test tones, the aforementioned impairments are measured by an envelope detector at the power amplifier output. Based on this information, the programmable digital IQ phase amplitude and offset controller (IQ_CTRL) in the BB circuit improves the TX image suppression from -32.4 to -42.6 dBc, and digital control signals generated by the on-chip self-healing controller heal the TX P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> and OIM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> from 9.5 to 13.2 dBm and from -32.5 to - 40 dBc, respectively. In terms of achieving the target specifications, namely, TX image suppression , , and , healing increases yield on ten dies from 0% to 100%. The BB circuit consumes only 49 mW, of which 37 mW comes from the DACs and 12 mW from the DDFS and the IQ_CTRL.

Arbitrary Waveform Generator Based on Improved DDS Technology

This article describes an arbitrary waveform generator based on DDS (Direct Digital frequency Synthesis) technology. The arbitrary waveform generator can easily generate DC, square wave, sine wave or any other arbitrary waveform in mill volt or even microvolt level. The generator uses ARM and 51MCU dual-processor system framework. In the system design, we use multiple reference frequency source and dynamically generated waveform data method to generate waveform, which can effectively improve the stability and reduce the distortion of the output waveform.

The Design of Signal Generator of Electrical Fast Transients Burst

With the improvement of output frequency of electric fast transients (EFT) burst generator, amplitude attenuation of pulse train appeared in the high frequency. Therefore, the method of pulse width programmed digitally ,and realized by Field Programmable Gate Array (FPGA) device was put forward to overcome burst amplitude attenuation. The technology of direct digital frequency synthesis was used to adjust the output signal frequency changes. The linear array memory with one bit was adopted to store square-wave waveform, the output signal duty cycle is digital adjustable, which is achieved by changing the waveform data in the linear array memory. Brust generator is designed by using VHDL languages in the QUARTUS II 6.0 simulation platform. The simulation and experiment results show that when the frequency of the output signal reaches 1 MHz, frequency resolution arrives at 6Hz, error of pulse width is less than 10 ns.

A Signal Generator Based on AD9850

This paper analyzes the advantages of the direct digital frequency synthesis (DDS) in signal generator applications, introduces the basic principles and characteristics of AD9850, a cost-effective chip, shows the overall scheme of a signal source design based on DDS and implements the hardware system. Experimental results show the signal generator can produce sine wave signals scoping from 100Hz to 5MHz, clock signals and triangular wave signals and can display frequency on the LCD.