Abstract
The classical structure of linear interpolation-based phase-to-sine mapper (PSM) consists of at least two ROMs for polynomial coefficient storage. Other architectures may include extra ROM for storing residual errors. However, ROMs dissipate high power and occupy a significant amount of the die area. This study presents a new technique that eliminates the ROM by including the computation of segment initial coefficients in the hardware. Therefore, it becomes possible to trim down noticeable hardware resources. The proposed direct digital frequency synthesizer (DDFS) architecture has been encoded in VHDL and synthesized with Quartus II software. Post simulation results show that the proposed design is capable of achieving the theoretical spurious-free dynamic range (SFDR) upper bound when optimal polynomial coefficients are considered. For 32 piecewise linear segments, the SFDR of the synthesized sinusoid is 84.15 dBc. A ROM compression ratio of 597.3:1 was also achieved. The performance of the DDFS is compared with previously presented DDFS techniques and the results show that the proposed design has advantages of high ROM compression ratio and low hardware complexity. DOI: http://dx.doi.org/10.5755/j01.eee.19.10.5905
Highlights
Direct digital frequency synthesizers (DDFSs) are capable of producing sine output waveforms with ultra-thin frequency increments, fast frequency switching, and high spectral purities
The synthesized signal is primarily digital in the DDFS; the DDFS can be incorporated with different digital modulations because of the ease in handling the frequency, phase, and amplitude in the digital domain
The initial coefficients are successfully replaced by accumulated pervious slope coefficients, allowing the ROM to be replaced with a simple accumulator
Summary
Direct digital frequency synthesizers (DDFSs) are capable of producing sine output waveforms with ultra-thin frequency increments, fast frequency switching, and high spectral purities. During the last four decades, considerable modifications have been introduced and numerous alternative architectures have been proposed to reduce the computational complexity of the PSAC. These methods can be categorized under three major groups; ROM compression [3]–[5], angle rotation [6]–[8], and piece-wise polynomial interpolation methods [9]–[11]. A generic PSAC structure based on the linear interpolation technique comprises two ROMs for storing segment initial amplitudes and segment slope coefficients. Once the ROM is eliminated, we expect the target system to exhibit excellent spectral purity and low power consumption with reasonable hardware overhead
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