Direct Digital Frequency Synthesizer Research Articles

Vhdl Implementation Of Ds Ss-cdma Transmitter And Receiver For AD Hoc Network

In past few years, lot of research is performed in both industries and academics into the development of CDMA. In DS-SS CDMA multiple signal channels occupy the same frequency band being distinguished by the use of different spreading codes. Digital cellular telephone system and personal communication system uses CDMA communication. In this project direct sequence spread spectrum principle based code division multiple access (CDMA) transmitter and receiver is implemented in VHDL for FPGA. The transmitter module mainly consists of data generator, programmable chip sequence generator (PN sequence generator), direct digital frequency synthesizer (DDFS), BPSK modulator blocks. The receiver modular mainly consists of BPSK demodulator, programmable chip sequence generator (PN sequence generator), matched filters, threshold detector blocks. Modelsim Altera 13.1 tool will be used for functional and logic verification at each block. The Xilinx synthesis technology of Xilinx ISE 9.2i tool will be used for synthesis of transmitter and receiver on FPGA Spartan 3E. A transmitter and Receiver components have been designed individually using Bottom-up approach. The designs then are combined and defined by component declaration and port mapping. This project concentrates on application of VHDL simulation and FPGA compiler to Wireless Data components..

Design of Modulator and Demodulator for a 863-870 MHz BFSK Tranceiver

This paper presents the design of low power modulator and demodulator circuits dedicated to a BFSK transceiver, operating in the 863- 870 MHZ ISM band. The two circuits were designed using ams 0.35µm technology with 3V dc voltage supply. Simulation results of the new Direct Digital Frequency Synthesizer in the modulation have shown good performances of the designed system as the Spurious Free Dynamic Range SFDR reached -88 dBc while the circuit consumes only 47.7 µW @ 43.3MHz. The demodulator has also presented a good BER of 10-3 @10.9 EbtoN0 and a sensitivity of about -115 dBm.

An Enhanced Adaptive Recoding Rotation CORDIC

The Conventional Coordinate Rotation Digital Computer (CORDIC) algorithm has been widely used in many applications, particularly in Direct Digital Frequency Synthesizers (DDS) and Fast Fourier Transforms (FFT). However, CORDIC is constrained by the excessive number of iterations, angle data path, and scaling factor compensation. In this article, an enhanced adaptive recoding CORDIC (EARC) is proposed. It uses the enhanced adaptive recoding method to reduce the required iterations and adopts the trigonometric transformation scheme to scale up the rotation angles. Computing sine and cosine is used first to compare the core functionality of EARC with basic CORDIC; then a 16-bit DDS and a 1,024-point FFT based on EARC are evaluated to demonstrate the benefits of EARC in larger applications. All the proposed architectures are validated on a Virtex 5 FPGA development platform. Compared with a commercial implementation of CORDIC, EARC requires 33.3% less hardware resources, provides a twofold speedup, dissipates 70.4% less power, and improves accuracy in terms of the Bit Error Position (BEP). Compared to the state-of-the-art Hybrid CORDIC, EARC reduces latency by 11.1% and consumes 17% less power. Compared with a commercial implementation of DDS, the dissipated power of the proposed DDS is reduced by 27.2%. The proposed DDS improves Spurious-Free Dynamic Range (SFDR) by nearly 7 dBc and dissipates 21.8% less power when compared with a recently published DDS circuit. The FFT based on EARC dissipates a factor of 2.05 less power than the commercial FFT even when choosing the 100% toggle rate for the FFT based on EARC and the 12.5% toggle rate for the commercial FFT. Compared with a recently published FFT, the FFT based on EARC improves Signal-to-Noise Ratio (SNR) by 8.9 dB and consumes 7.78% less power.

Design of an experimental platform to investigate the effects of audible sounds on plant growth

An experimental platform was developed to investigate the effects of audible sound (20 Hz to 20 MHz) on plant growth promotion, which included a microcontroller-based embedded system for audible sound adjustment and analysis. The direct digital frequency synthesis (DDFS) method was used to generate various waveforms of sound in the platform. Soundproof glass and mufflers were used to reduce background noise. The developed system was tested on various plants, including hydroponic tomatoes, celery and mung bean. The testing results showed that the developed platform could produce pure tone and mixing audible sound with high stability and accuracy, make octave analysis of the sound under experimental environments, and the background noise in the testing chamber of the platform was lower than 55 dB(A) when the compression engine was working. The developed experimental platform has a great potential on facilitating scientific research on acoustic biology effects on plants and collecting real-time experimental data. Keywords: plant growth, background noise, acoustic biology effect, direct digital frequency synthesis, sound sensor DOI: 10.3965/j.ijabe.20150805.1556 Citation: Cai W M, Zhu S M, Wang N, He H N, Ying B H. Design of an experimental platform to investigate the effects of audible sounds on plant growth. Int J Agric & Biol Eng, 2015; 8(5): 162－169.

Analysis of Phase Truncation Error Based on Multi-Path Pseudo-Interleaved Direct Digital Frequency Synthesis

Low output frequency and spurs are main imperfections in direct digital frequency synthesis (DDFS). For increasing output frequency determined by sampling rate, the structure of multi-path pseudo-interleaved DDFS is proposed. However, it introduces more complex phase truncation error than single path DDFS. In order to analyze the effect of phase truncation error, the model of pseudo-interleaved DDFS with phase truncation is established. Based on the model, the distribution and amplitude of spur caused by phase truncation are discussed and calculated. Then some important conclusions are drawn and proved by experiment, which can provide theoretical supports for spurious performance evaluation and parameter selection while designing signal source or clock generator based on pseudo-interleaved DDFS.

A high speed direct digital frequency synthesizer based on multi-channel structure

This paper presents a direct digital frequency synthesizer (DDFS) for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 × 0.98 mm2 and total power consumption of 300 mW at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.

Design of a ROM-Less Direct Digital Frequency Synthesizer on FPGA

Design of a ROM-Less Direct Digital Frequency Synthesizer on FPGA

Design and implementation of a multiband digital filter using FPGA to extract the ECG signal in the presence of different interference signals

In this paper, we propose a practical way to synthesize and filter an ECG signal in the presence of four types of interference signals: (1) those arising from power networks with a fundamental frequency of 50Hz, (2) those arising from respiration, having a frequency range from 0.05 to 0.5Hz, (3) muscle signals with a frequency of 25Hz, and (4) white noise present within the ECG signal band. This was done by implementing a multiband digital filter (seven bands) of type FIR Multiband Least Squares using a digital programmable device (Cyclone II EP2C70F896C6 FPGA, Altera), which was placed on an education and development board (DE2-70, Terasic). This filter was designed using the VHDL language in the Quartus II 9.1 design environment. The proposed method depends on Direct Digital Frequency Synthesizers (DDFS) designed to synthesize the ECG signal and various interference signals. So that the synthetic ECG specifications would be closer to actual ECG signals after filtering, we designed in a single multiband digital filter instead of using three separate digital filters LPF, HPF, BSF. Thus all interference signals were removed with a single digital filter. The multiband digital filter results were studied using a digital oscilloscope to characterize input and output signals in the presence of differing sinusoidal interference signals and white noise.

VLSI Design and Implementation of Efficient Software Defined Radio Using Optimized Quadrature Direct Digital Frequency Synthesizer on FPGA

Abstract This paper presents an framework for efficient design and implementation of software defined radio (SDR) on FPGA platform using optimized Quadrature Direct Digital Frequency Synthesizer (QDDFS). An basic SDR System consists of RF Antennas, Analog to Digital converter (ADC), Digital to Analog converter (DAC), Filters and processing units. Reconfigurability and optimization can be achieved in the processing unit to a maximum extent. Processing unit of the SDR System is designed and implemented completely in this paper. The important parts of the SDR system designed are 16-Quadrature Amplitude Modulation (16-QAM), Orthogonal Frequency Division Multiplexing (OFDM) (16 point Fast Fourier Transforms (FFT), Inverse Fast Fourier Transform (IFFT) and Cyclic Prefix) and QDDFS. QDDFS generates the sine and cosine values in digital domain and it is optimized in terms of the device utilization with efficient performance and the functionality of rapidly hopping between the different frequencies, faster response time are also achieved. Both in transmitter and receiver, the same QDDFS architecture is used. The Input to the SDR system designed is Text Data which is fed and retrieved in the ASCII Format.

Design of DDS Based on FPGA Technology

This paper introduces the working principle and structure of direct digital frequency synthesizer. This paper select the technology of lookup table to design DDS because it has many advantages such as less consumption hardware resources, simple structure, output only small delay and so on. As a result, signal generator can produce many waveforms with good stability and high frequency resolution. Finally, test showed that the output wave of triangular signal frequency is greater than 1MHz and the highest sine wave frequency is 30MHz, the value of peak to peak is continuously adjustable in 50mV ~ 4V range. The result of study will provide theoretical guidance for the design of DDS.

A 2.5-GHz direct digital frequency synthesizer in 0.18 μm CMOS

A 2.5 GHz direct digital frequency synthesizer (DDS) in 0.18 μm CMOS is presented. This DDS has a 32 bit phase word and uses an optimized excess-four Coordinated Rotation Digital Computer (CORDIC) arithmetic to achieve phase to amplitude conversion (SFDR as 113 dB). A time interleaved architecture is used to achieve 2.5 GHz high speed. Fundamental principle of CORDIC and four practical considerations in circuit implementation are also presented. This 2.5 GHz DDS (with an embedded 14 bit current steering DAC) is implemented in a 0.18 μm CMOS technology, occupies 4.6 mm × 4.2 mm including bond pads. Measured performance is SFDR >58 dB (spur cancelled) and narrowband SFDR >84 dB for output signal frequencies up to 1 GHz.

A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS

Direct-digital frequency synthesizers (DDFSs) have been employed in many frequency-agile communication systems because of their wide bandwidth, fine frequency resolution, and fast frequency-hopping characteristics. Recent developments in DDFSs are towards enhancing performances through reduction of both complexity and power consumption [1-3]. The segmented nonlinear DAC (NLDAC) structures in [1,2] require additional coarse phase information for fine amplitude decoding with a complex decoder. Moreover, the quarter-sine-wave technique incorporated into the segmented NLDACs in [1,2] degrades spectral purity due to the need of the MSB shift DAC that introduces additional offset. Another scheme in [3] reduces complexity and power consumption by replacing the digital-based phase-to-amplitude converter with an analog-based converter, resulting in limited spectral purity. Unlike previous schemes, this work presents comprehensive enhancements in all key areas of a DDFS, the pipelined phase accumulator (PACC), digital decoder, and NLDAC as shown in Fig. 21.3.1. First, the low-power PACC with multi-level momentarily activated bias (M2AB) is presented to reduce power dissipation. Second, the coarse phase-based consecutive fine-amplitude grouping (C2FAG) scheme reduces the hardware complexity and the power consumption in digital decoder circuits. Third, the mixed-wave conversion topology (MCT) in the NLDAC improves the output spectral purity.

Design of linear sweep source based on DDS used in readout system for wireless passive pressure sensor

This paper proposes the design and research on the high bandwidth linear frequency sweep signal source involved in the readout unit module of the wireless passive pressure sensor in high temperature based on the principle of mutual inductance coupling which is applied widely at present. The operating principle of the linear sweep frequency source based on the direct digital frequency synthesis (DDS) technology is introduced, and the implementation method of the hardware circuit and logic sequential control process required in our system has been realized utilizing this technology. Through the experiments under different conditions of the step value, the sweep range and other related design indicators, the influence on the extraction method of resonance frequency information, extraction accuracy, and others during the readout system of the mutual inductance coupling sensor are analyzed and studied. The design of the linear frequency sweep signal source is realized with a resonance frequency change resolution of 6 kHz, a minimum step value of 1 kHz, and a precision of frequency for 0.116 Hz within the sweep width of 1 MHz–100 MHz. Due to the use of the integrated commercial chip, the linear sweep frequency source is made small in size, high working frequency, high resolution and low step values for the readout unit modularized of a higher application value.

Design and Simulation of Signal Generator Based on FPGA

The article introduced the basic structure and the realization principle of direct digital frequency synthesizer (DDS), and analyzed main properties of DDS system, compared the different ways to achieve frequency synthesis to determine the design scheme in this paper. In addition to the realization of general waveform, the output of the system can realize any hand-painted waveform, improve the shortcomings of the current function generator, and also has the advantages of low cost, low power consumption, short development cycle, flexible design, has the very good practical value and broad application prospect.

Design of Tunable F-P Filter Driver Based on FPGA

The special driver for tunable F-P filter is expensive, so it has an important application value to design a driver with stable performance and low cost. In this paper, the field programmable gate array (FPGA) was chosen as the core chip to constitute triangular signal generator based on direct digital frequency synthesizer (DDS). The output frequency of waveform ROM look-up table will be altered by changing frequency control word. Then, the products of amplitude word and signals of ROM table output were transmitted to DAC to be converted into analog signal. The variable frequency and amplitude modulation signals were got after smoothed by low pass filter. The frequency range of driving signal is 1 Hz~10 KHz, and the resolution of frequency is 0.1 Hz. The amplitude range is 1 V~10 V, and the resolution of amplitude is 0.1 V. The simulation and experimental results show that the driver has the characteristics of simple structure, stable signal, adjustable frequency and amplitude and lower cost. It can satisfy the requirements of tunable F-P filter driven in practical engineering.

A direct digital synthesizer of compound wideband signals

Principles of construction and structural and circuit designs of direct digital synthesizers based on the method of direct digital frequency and signal synthesis are described. The block and circuit diagrams of the direct digital synthesizer of compound wideband signals are presented. This synthesizer is used to synthesize signals with the amplitude, frequency, and phase modulation in a frequency range from 0.001 to 200MHz.

Design of Dual-channel Sine Wave Generator with Tunable Phase Difference

Signal source is an important part of modern electronic system and has a wide range of applications in the fields of communication, measuring & control, navigation and medical care. This project developed a new dual-channel sine wave generator with Tunable Phase Difference on the basis of the direct digital frequency synthesis (DDS) technology. Design was accomplished using STC89C52 MCU and FPGA as the control center, integrating basic operation circuit and employing low-pass filter and the necessary software algorithm. The experimental results showed that the system can produce dual sine waves with tunable phase difference in 0~359° range. The system is stable in work and it is easy to adjust parameters.

Design of Dual High Precision High Resolution Frequency Synthesizer Based on AD9854

To obtain dual high-precision and high-resolution numerical control signal source, and accurately adjust the signal frequency, the paper proposed a method based on AD9854 direct digital frequency synthesis technology, design and implementation the dual high-precision and high-resolution frequency synthesizer. FPGA controlled AD9854 registers to achieve frequency modulation, and after amplification processing output by THS3001, increasing the output signal drive capability. Comprehensive consideration the anti-jamming measures, the system is stable and reliable, the output signal frequency range from 500Hz to 30MHz relative error is less than 10ppm, and can numerical adjust the sine and square wave frequency and has a sweep output mode. Compared with previous equipment, it reduces the system power consumption and volume.

Investigation of Phase-Shifting and Frequency Conversion Sinusoidal Signal Generator Based on DDS and FPGA

The direct digital frequency synthesis (DDS) technology has high frequency resolution, fast frequency switching, low phase noise and higher frequency stability, so it is widely used in communications, aerospace, instrumentation and other fields. In this paper, the DDS system was designed based on Field Programmable Gate Array (FPGA) and hardware design language (VHDL). The experimental and simulation results show that the system has stable output frequency, high frequency accuracy, adjustable frequency and phase.

A center frequency adjustable narrow band filter for the detection of weak single frequency signal.

We describe and implement a center frequency adjustable narrow band filter based on the crystal filter for the detection of weak single frequency signal. It is formed by a multiplier, a direct digital frequency synthesizer, a multi-stage crystal bandpass filter, and a micro control unit which is used to set the center frequency of the filter. A theoretical study is proposed and experimentally validated. The test results show that the 3 db and 20 db bandwidths are 0.84 Hz and 2.73 Hz, respectively, and the filter system can effectively detect the signal with amplitude below 1 μV and a frequency which ranges from 10 Hz to the frequency that is mainly limited by the components applied.