Digitally Controlled Oscillator Research Articles

A CMOS based low power digitally controlled oscillator design with MOS varactor

With the shift from traditional analog circuit designs to an all-digital intensive approach, the all-digital Phase-locked loops (ADPLLs) have become more attractive in digital communication systems. Digitally controlled oscillators (DCO) are the key components of the ADPLL circuits. In this paper, a new low power DCO structure is proposed with NMOS transistor as the switching network and utilizing the NMOS varactor as shunt-capacitive loads for the delay cells. The new DCO is capable of producing much higher output frequencies and comprises of components that are fully digital. The proposed DCO structure is designed for three, five and seven stages in CMOS 0.18 µm technology. Variable capacitance is achieved by the use of control word which is applied through NMOS switches conditionally selecting combinations of capacitance and hence determining the delay of the circuit. A 3-stages digitally controlled oscillator shows output frequency variation from 1.986 to 3.526 GHz with a power consumption of 1.484 mW. In the 5-stages DCO, the output frequency varies from 1.154 to 2.210 GHz with a power consumption of 2.762 mW. For 7-stages DCO, the output oscillation frequency is in the range from 0.835 to 1.658 GHz with a power consumption of 4.04 mW. A 3-stages DCO shows a phase noise of − 100.06 dBc/Hz with the offset of 1 MHz with the corresponding figure of merit (FoM) of 165.37 dBc/Hz. Five and seven-stages DCO show phase noise of − 102.08 dBc/Hz and − 105.52 dBc/Hz at 1 MHz respectively. The figure of merit (FoM) for 5 and 7-stages is 160.92 dBc/Hz and 159.07 dBc/Hz respectively. The digital tuning range for 3, 5, and 7-stages DCO is 55.96%, 62.78%, and 66.05% respectively. Further, the results show that the designed DCO has a maximum supply voltage tuning range of 101.45% with the variation of VDD from 1 to 1.8 V. Comparison with earlier reported circuits has been made based on output frequency, power consumption, and phase noise.

A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration

This paper presents a low-jitter, injection-locked frequency generator that can provide multiple output frequencies concurrently. The injection-locked digitally controlled oscillators (DCOs) can be controlled separately so that their output frequencies can be changed independently between 0.9 and 1.2 GHz in 15-MHz steps. Due to the proposed time-interleaved frequency calibrator that operates continuously in the background, all injection-locked DCOs are ensured to maintain excellent jitter performance against process, voltage, and temperature (PVT) variations. As a prototype, the proposed injection-locked, multi-frequency generator (ILMFG) was designed to generate two independently controlled output signals, and it was fabricated in a 65-nm CMOS technology. The 1-MHz phase noise and the rms jitter integrated from 1 kHz to 40 MHz of the 960-MHz output signal were −133.5 dBc/Hz and 375 fs, respectively. The degradation of rms jitter was restricted to less than 10%. The silicon area was 0.05 mm2, and the total power consumption was 7.7 mW when generating two different output frequencies.

A 2.9 GHz Variable Inductor-Based DCO With 1.3 kHz Frequency Resolution for FMCW Radar Applications

A high-resolution digitally controlled oscillator (DCO) for frequency-modulated continuous-wave radar applications is presented in this brief. The proposed DCO utilizes a variable inductor and linearization correction technique, and cooperates with the multi-stage frequency multipliers to achieve frequency sources at 2.9, 5.8, and 11.6 GHz simultaneously on a single chip. The demonstration of the proposed DCO and frequency multipliers was fabricated in 1P10M 40-nm CMOS technology. Measurement results show that the frequency resolution of the DCO achieves 0.73 to 1.3 kHz over a frequency range of 16.8%, from 2.5 to 2.96 GHz. The phase noise at 1-MHz frequency offset is −127.3 dBc/Hz with 15-mW power consumption. The chip occupies 0.73 mm2, while the proposed DCO occupies a core area of 0.31 mm2.

A Low-Noise Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

In this paper, we propose a 60-GHz fractional- ${N}$ digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker ( $1/\!f^{3}$ ) and thermal ( $1/\!f^{2}$ ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while canceling the 20-GHz fundamental. The latter component is fed back to the frequency dividers in an all-digital phase-locked loop for phase detection, which comprises a pair of digital-to-time and time-to-digital converters with $\Sigma \Delta $ dithering to attenuate fractional spurs. The mechanism of flicker noise upconversion to $1/\!f^{3}$ PN in the DCO is investigated, and a reduction technique is proposed. The 28-nm CMOS prototype achieves 213–277-fs rms jitter in the 57.5–67.2-GHz tuning range while consuming only 40 mW. The DCO flicker PN corner is record low at 300–400 kHz.

A Full Digital Fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math> </inline-formula> TAF-FLL for Digital Applications: Demonstration of the Principle of a Frequency-Locked Loop Built on Time-Average-Frequency

Time-average-frequency (TAF) is a novel concept proposed in 2008 for constructing clock signal. TAF direct period synthesis (TAF-DPS) is an emerging frequency synthesis technique based on TAF. Its distinguished features are small frequency granularity and fast frequency switching, achieved simultaneously for a given design. Furthermore, its output frequency is monotonically changed with a digital control word. Those features make it suitable digitally controlled oscillator (DCO). In this paper, a TAF-DPS DCO is created entirely from digital cells. Using it as the core, a 100% digital TAF frequency-locked loop (TAF-FLL) is constructed. Unlike all established FLL and PLL architectures, TAF-FLL’s output is in TAF instead of conventional frequency. This fact impacts the design from at least two directions. First, it blurs the boundary between integer- and fractional-N. Second, the issues of output jitter and the loop design are independent of each other and can be treated separately. This novel all-digital architecture has been implemented in field-programmable gate array for verifying the principle. It is the first case of building frequency control loop on TAF. The purpose of this TAF-FLL is to drive digital circuits, for digital-oriented applications.

Design and Analysis of a DCO-Based Phase-Tracking RF Receiver for IoT Applications

This paper presents an energy-/area-efficient digitally controlled oscillator (DCO)-based phase-tracking Receiver for Internet-of-Things (IoT) applications. The RX leverages the constant-envelope nature of frequency shift keying modulation adopted in many IoT protocols, e.g., IEEE802.15.4 and Bluetooth low energy (BLE), to enhance the energy efficiency and to reduce the chip area. The proposed RX, with the DCO acting as a local oscillator (LO) and binary frequency feedback, promotes low-power and low-voltage circuit design, while a data-aided carrier-frequency tracking ensures the received carrier stability without a power-/area-hungry phase-locked loop (PLL). The RX avoids a compromise between a power-hungry I/Q LO generation and the image rejection in traditional RXs. An equivalent mathematical model is further presented, which helps to analyze and optimize the frequency response of the proposed RX. Fabricated in 40-nm CMOS, the RX consumes 1.55 mW from a 0.85-V supply and has a −87-dBm sensitivity at 2 Mb/s, which leads to a 0.77-nJ/b energy efficiency and 178-dB RX sensitivity FoM.

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits

This paper proposes a synthesized injection-locked bang-bang phased-locked loop (SILBBPLL) with high digital controlled oscillator (DCO) frequency resolution. The SILBBPLL is expressed with hardware description language and automatically placed & routed (APR) by using standard digital circuit design flow. As the mismatch issues of the circuits are not considered carefully during the APR design flow, the phase noise performance is severely deteriorated. We adopt pulse injection locking technique to improve the phase noise performance. The DCO frequency resolution is critical for reducing the reference spur in a digital injection-locked PLL. Therefore, we propose novel frequency tuning circuits to increase the DCO frequency resolution so that the reference spurs are reduced. The frequency tuning circuits consist of a standard cell based high-linearity output feedback DAC (OFDAC) and two custom varactors. The OFDAC is used to tune the frequency of the DCO with the custom varactor precisely. The custom varactor is firstly designed, added into the standard cell library, and APR with the standard cells. The SILBBPLL chip with a core area of 0.008 mm2 is implemented in 65 nm CMOS process. When operating at 1.8 GHz, the measured results show that the root-mean-square (RMS) jitter integrated from 10 kHz to 100 MHz is 1.1 ps, and the power consumption is 1.5 mW with a 0.8-V supply. The proposed SILBBPLL achieves a figure-of-merit (FoM) of −237.4 dB and a reference spur of −50.9 dBc.

An 82–107.6-GHz Integer-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math> </inline-formula> ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta–Sigma TDC

A W-band integer-N all-digital phase-locked loop (ADPLL) aiming for wide frequency tuning range (TR) and low phase noise is proposed. The W-band ADPLL employs a digitally controlled oscillator (DCO) with split transformer and dual-path exponentially scaled switched-capacitor ladder and a clock-skew-sampling delta-sigma time-to-digital converter (TDC). The 65-nm CMOS W-band ADPLL measures a frequency TR of 27% from 82 to 107.6 GHz and phase noise from -106 to -110 dBc/Hz at 10-MHz offset and -84 to -87 dBc/Hz at 100-kHz offset while consuming 35.5 mW and occupying a 0.36 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area, corresponding to a figure of merit (FOM) of -171 ~ -173 dB and FOMT of -178 ~ -181 dB.

A 0.0043-mm2 0.3–1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDC

This paper presents a synthesized fractional-N digital phase-locked loop (PLL) with a speculative dual-referenced interpolating time-to-digital converter (DI-TDC). The DI-TDC measures a fractional phase by referencing two adjacent quadrant boundaries which are given by a four-phase digitally controlled oscillator (DCO). It achieves a robust gain matching to the first order without need of any calibration. By predicting a time region of interest for the next TDC conversion, the power and area overheads for DI-TDC is minimized. Except for DCO and a reference delay chain, the PLL is implemented with register-transfer level (RTL) behavioral descriptions followed by an automated synthesis. It is fabricated in 28-nm CMOS with an active area of 0.0043 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The PLL shows a wide frequency lock range operating at a supply voltage from 0.3 to 1.2 V, achieving a stable figure-of-merit of better than -220 dB for a supply voltage above 0.6 V.

Structure of All-Digital Frequency Synthesiser for IoT and IoV Applications

In recent years number of Internet of Things (IoT) services and devices is growing and Internet of Vehicles (IoV) technologies are emerging. Multiband transceiver with high performance frequency synthesisers should be used to support a multitude of existing and developing wireless standards. In this paper noise sources of an all-digital frequency synthesiser are discussed through s-domain model of frequency synthesisers, and the impact of noise induced by main blocks of synthesisers to the overall phase noise of frequency synthesisers is analysed. Requirements for time to digital converter (TDC), digitally controlled oscillator (DCO) and digital filter suitable for all-digital frequency synthesiser for IoT and IoV applications are defined. The structure of frequency synthesisers, which allows us to meet defined requirements, is presented. Its main parts are 2D Vernier TDC based on gated ring oscillators, which can achieve resolution close to 1 ps; multi core LC-tank DCO, whose tuning range is 4.3–5.4 GHz when two cores are used and phase noise is −116.4 dBc/Hz at 1 MHz offset from 5.44 GHz carrier; digital filter made of proportional and integral gain stages and additional infinite impulse response filter stages. Such a structure allows us to achieve a synthesiser’s in-band phase noise lower than −100 dBc/Hz, out-of-band phase noise equal to −134.0 dBc/Hz and allows us to set a synthesiser to type-I or type-II and change its order from first to sixth.

A low-jitter all-digital PLL with high-linearity DCO

This paper describes a low-jitter all-digital phase-locked loop (ADPLL) with a high-linearity digitally controlled oscillator (DCO). The proposed DCO consists of a three-stage differential ring oscillator with a coarse-tune stage, a fine-tune stage, and process voltage temperature (PVT) variation compensation. The coarse-tune stage comprises tri-inverters controlled using the binary-weighted method and has high linearity and monotonicity. The fine-tune stage consists of six groups of NMOS capacitors to achieve a high timing resolution. Moreover, the range of the DCO frequency can be varied according to the PVT variations s to match the desired frequency range of the ADPLL. The proposed ADPLL was implemented in a 0.18-µm standard CMOS process with a supply voltage of 1.8 V. The experimental results indicated that the proposed DCO can cover the frequency range of 202–518 MHz under different PVT variations. The output frequency range of the proposed ADPLL with a programmable divider was 402–417 MHz, and its division range was 134–139. The ADPLL is suitable for MedRadio band applications. At 411 MHz, the power consumption was 13 mW, rms jitter was 5.98 ps (0.25% of the output period), and active die area was 0.27 mm2.

A 0.0129 mm2 DPLL With 1.6~2.0 ps RMS Period Jitter and 0.25-to-2.7 GHz Tunable DCO Frequency Range in 55-nm CMOS

The proposed digital phase locked loop uses a time-to-digital converter with associated simple algorithm to improve jitter performance. The wide frequency tuning is achieved through three different loop delay control schemes of the digital controlled oscillator (DCO). Verified in GLOBALFOUNDRIES 55 nm LPX process, the chip occupies 0.0129 mm2, achieves a wide range of 250 MHz to 2.7 GHz, and consumes only 1.1 mW when DCO’s frequency is 500 MHz. The phase locked loop output clock jitter is around 1.6–2.0 ps.

A CMOS Dual-&lt;italic&gt;RC&lt;/italic&gt; Frequency Reference With ±200-ppm Inaccuracy From −45 °C to 85 °C

This paper presents a 7-MHz CMOS RC frequency reference. It consists of a frequency-locked loop in which the output frequency of a digitally controlled oscillator (DCO) is locked to the combined phase shifts of two independent RC (Wien bridge) filters, each employing resistors with complementary temperature coefficients. The filters are driven by the DCO’s output frequency and the resulting phase shifts are digitized by high-resolution phase-to-digital converters. Their outputs are then combined in the digital domain to realize a temperature-independent frequency error signal. This digitally assisted temperature compensation scheme achieves an inaccuracy of ±200 ppm from –45 °C to 85 °C after a two-point trim. The frequency reference draws 430 $\mu \text{A}$ from a 1.8-V supply, while achieving a supply sensitivity of 0.18%/V and a 330-ppb Allan deviation floor in 3 s of measurement time.

All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply

In this paper, we introduce an all-digital phase-locked loop (ADPLL) for Bluetooth low energy (BLE) that eliminates the need for a crystal oscillator (XO) other than a 32.768-kHz real-time clock (RTC) already present in wireless systems. Specifically, we propose to replace the conventional channel settling with a band settling that would be carried out only once per global device power up. The ADPLL locks to the center of the Bluetooth band (2440 MHz) upon system power-up and jointly performs an instantaneous channel hopping and Gaussian frequency shift keying (GFSK) modulation in a two-point manner to overcome the narrow PLL bandwidth (BW) due to the 32.768-kHz reference. Extensive calibrations linearize the effective cubic digitally controlled oscillator (DCO) transfer function to achieve a precise frequency range of hopping and modulation. Realized in 16-nm FinFET, it consumes <1 mW at ≤0.45 V, while achieving best-in-class performance and <100-ns hopping time.

A 23-GHz Low-Phase-Noise Digital Bang–Bang PLL for Fast Triangular and Sawtooth Chirp Modulation

Frequency-modulated continuous-wave (FMCW) radars with high resolution require the generation of low-phase-noise, low-spurs, and highly linear chirp signals with large peak-to-peak value (chirp bandwidth) and a short period of the modulation signal [1]. In radar systems, the spot phase noise of the chirp generator is converted to the intermediate frequency of the receiver making it difficult to detect two close targets, while spurs cause the detection of false targets. For those reasons, medium-range radar applications in the 77-to-81GHz band typically specify spot phase noise lower than −90dBc/Hz at 1MHz offset and spur level below −50dBc. Unlike triangular chirps, saw-tooth chirps allow for a reduced dead time for range detection. However, any practical modulator needs a finite time (idle time) to make a large frequency jump at the end of the saw-tooth, and this limits the duty cycle of the saw-tooth. For instance, a fast saw-tooth chirp with 200kHz rate and 95% duty cycle leaves the idle time of only 250ns. Fractional-N PLLs can be used as chirp modulators. Unfortunately, low phase noise and spur levels require a narrow PLL bandwidth, while short idle time demands for a wide one. The two-point injection of the modulation signal, both from the modulus control of the divider and the tuning input of the voltage-controlled oscillator (VCO), is a known method to simultaneously achieve a narrow PLL bandwidth and fast modulation. However, even in that scheme, a frequency modulation error is mainly limited by gain mismatch between the two injection paths and by the linearity of the VCO [2]. In this work, a 20-to-24GHz digital bang-bang PLL, which uses the two-point modulation scheme to generate triangular and saw-tooth chirp signals, is presented. Unlike previous works [1-4], this architecture is able to generate fast saw-tooth chirps with the slope up to 173MHz/js, the idle time below 200ns, and the rms frequency error of better than 0.06%. The gain mismatch between the two modulation paths are automatically calibrated by a digital algorithm [5], and the input of the digitally controlled oscillator (DCO) is pre-distorted via an automatic background correction scheme, which compensates for the DCO nonlinearity.

A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture

A novel digital-intensive hybrid transmitter (TX) architecture is presented, combining conventional inphase and quadrature (I/Q) with constrained phase modulation. The proposed architecture utilizes an RF-DAC with phase modulated RF clock and adjusted I/Q components. By incorporating phase modulation the quadrature component is kept small while the inphase component approaches the complex signal envelope. Compared to a digital-quadrature TX architecture this results in a significantly reduced average and peak RF-DAC cell utilization. Therefore, the RF-DAC can be operated in less back-off at higher average output power and drain efficiency. The phase modulation is constrained in order to relax the phase modulators system requirements. Compared to a digital polar TX architecture utilizing an RF digital phase-locked loop with two-point phase modulation, this results in reduced frequency modulation and digital-controlled oscillator tuning range requirements. In addition, the design effort is further shifted from analog to digital domain in order to better exploit the benefits of CMOS technology scaling.

A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique.

Herein, we present a low-power cyclic Vernier two-step time-to-digital converter (TDC) that achieves a wide input range with good linearity. Since traditional approaches require a large area or high power to achieve an input range >300 ns, we solve this problem by proposing a simple yet efficient TDC suitable for time-of-flight (TOF) sensors. In previous studies using the cyclic structure, the effect of startup time on the linearity of the TDC is not described. Thus, the achievable linearity has been limited when the TDC is used for applications requiring a high input range. We solve this problem by using a simple yet effective technique to compensate. The proposed technique is realized using (1) digitally-controlled oscillators (DCOs) that have dual frequency control and matched startup time; (2) an alignment detector that performs startup time correction by proper timing control; and (3) a fully symmetric arbiter that precisely detects the instant of edge alignment. To achieve a fine resolution for the cyclic Vernier TDC, we design two closely-matched DCOs with dual frequency control. The alignment detector performs the critical task of cancelling startup time via timing control. The detector is delay-compensated by using a dummy to provide matched loading for the two DCOs. To enhance the detection speed under low power, a current-reuse approach is employed for the arbiter. The TDC is fabricated using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process in a compact chip area of 0.028 mm2. Measured results show a dynamic range of 355 ns and a resolution of 377 ps. When the result is applied for TOF sensing, it corresponds to a distance range of 53.2 m and a resolution of 5.65 cm. Over a relatively large input range, good linearity is achieved, which is indicated by a DNL of 0.28 LSBrms and an INL of 0.96 LSBrms. The result corresponds to root mean square (RMS) error distance of 5.42 cm. The result is achieved by consuming a relatively low power of 0.65 mW.

An ADPLL-Based PSK Receiver for VHBR 13.56-MHz Contactless Smartcards and NFC Applications

This brief proposes an all-digital phase-locked loop (ADPLL) used as the phase-shift keying (PSK) receiver for a very high bit rate of 13.56-MHz smartcards. A detailed implementation from system to circuit level is presented. This ADPLL-based PSK demodulator mainly consists of a high dynamic range time to digital converter (TDC) without pulse shrinking effect, a dual-path digital loop filter, and a fine resolution digital controlled oscillator based on capacitor division without dithering. This design is fabricated by GF CMOS 40-nm technology with a core area of only 0.035 mm2. The measurement results show low current consumption of 40 mA for phase locking and 70 mA for PSK demodulation with 1.2-V supply. Both integral non-linearity and differential non-linearity of our TDC are smaller than 0.6 LSB. This prototype can demodulate 8-PSK at a symbol rate of 6.78 MHz, corresponding to a data rate of 20.34 Mb/s, with an energy efficiency of 4.1 pJ/bit.

Low supply voltage and multiphase all‐digital crystal‐less clock generator

A multiphase all-digital crystal-less clock generator (CLCG) with an interpolating digital controlled oscillator (DCO) that achieves an operating frequency of 500 MHz with 10-phase outputs is proposed. The CLCG adopts a specific temperature coefficient of a time-to-digital convertor (TDC) to create a positive or negative temperature coefficient and compensates for the DCO frequency drift. A time amplifier (TA) can extend the timing resolution of the TDC and reduce the effects of process variations in order to tune the TA gains. The frequency compensator adopts the frequency difference between the ring oscillator and DCO to reduce the frequency drift. The frequency accuracy is 69 ppm/°C from - 20 to 80°C. The root mean square jitter and output phase noise are 3.86 ps and - 100.36 dBc/Hz at 1 MHz, respectively. The core area of the test chip is 350 × 420 μm 2 in a 65-nm CMOS process. At a supply voltage of 0.6 V, the power consumption is 1.8 mW for the 5 Gb/s clocking system.

An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for <−107 dBc/Hz in-band phase noise while the 7.3-mW DCO emits −157 dBc/Hz at 20 MHz offset at 2 GHz. Reference spurs are <−91 dBc, while fractional spurs are <−55 dBc. The ADPLL supports a 2-point modulation and consumes 11.5-mW while occupying 0.22 mm2.